B2.102 TTBR0_EL3, Translation Table Base Register 0, EL3

The TTBR0_EL3 holds the base address of the translation table for the stage 1 translation of memory accesses from EL3.

Bit field descriptions

TTBR0_EL3 is a 64-bit register, and is part of the Virtual memory control registers functional group.

Figure B2-90 TTBR0_EL3 bit assignments
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RES0, [63:48]
RES0Reserved.
BADDR, [47:2]
Translation table base address.
RES0, [1]
RES0Reserved.
CnP, [0]

Common not Private. The possible values are:

0CnP is not supported.
1

CnP is supported.

Configurations

TTBR0_EL3 is mapped to AArch32 register TTBR0 (S). See B1.85 TTBR0, Translation Table Base Register 0.

RW fields in this register reset to architecturally unknown values.

Any of the fields in this register are permitted to be cached in a TLB.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

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