B2.109 VTCR_EL2, Virtualization Translation Control Register, EL2

The VTCR_EL2 controls the translation table walks required for the stage 2 translation of memory accesses from Non-secure EL0 and EL1.

It also holds cacheability and shareability information for the accesses.

Bit field descriptions

VTCR_EL2 is a 32-bit register, and is part of:

  • The Virtualization registers functional group.
  • The Virtual memory control registers functional group.
Figure B2-99 VTCR_EL2 bit assignments
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Bits[28:25] and bits[22:21], architecturally defined, are implemented in the core.

TG0, [15:14]

TTBR0_EL2 granule size. The possible values are:


All other values are not supported.


VTCR_EL2 is architecturally mapped to AArch32 register VTCR. See B1.91 VTCR, Virtualization Translation Control Register.

RW fields in this register reset to architecturally UNKNOWN values.

Bit fields and details that are not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

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