D3.9 EDITCTRL, External Debug Integration Mode Control Register

The EDITCTRL enables the external debug to switch from its default mode into integration mode, where test software can control directly the inputs and outputs of the core, for integration testing or topology detection.

Bit field descriptions

The ESITCTRL is a 32-bit register.

Figure D3-8 EDITCTRL bit assignments
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[31:1]
res0Reserved.
IME, [0]

Integration Mode Enable.

res0.The device does not revert to an integration mode to enable integration testing or topology detection.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

The EDITCTRL can be accessed through the external debug interface, offset 0xF00.

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