D6.8 PMPIDR1, Performance Monitors Peripheral Identification Register 1

The PMPIDR1 provides information to identify a Performance Monitor component.

Bit field descriptions

The PMPIDR1 is a 32-bit register.

Figure D6-7 PMPIDR1 bit assignments
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RES0, [31:8]
DES_0, [7:4]
0xBArm Limited. This is the least significant nibble of JEP106 ID code.
Part_1, [3:0]
0xDMost significant nibble of the performance monitor part number.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

The PMPIDR1 can be accessed through the external debug interface, offset 0xFE4.

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