D6.5 PMCIDR2, Performance Monitors Component Identification Register 2

The PMCIDR2 provides information to identify a Performance Monitor component.

Bit field descriptions

The PMCIDR2 is a 32-bit register.

Figure D6-4 PMCIDR2 bit assignments
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RES0, [31:8]
PRMBL_2, [7:0]
0x05Preamble byte 2.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

The PMCIDR2 can be accessed through the external debug interface, offset 0xFF8.

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