D8.31 TRCIDR2, ID Register 2

The TRCIDR2 returns the maximum size of six parameters in the trace unit.

The parameters are:

  • Cycle counter.
  • Data value.
  • Data address.
  • VMID.
  • Context ID.
  • Instruction address.

Bit field descriptions

The TRCIDR2 is a 32-bit register.

Figure D8-29 TRCIDR2 bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.

RES0, [31]
VMIDOPT, [30:29]

Indicates the options for observing the Virtual context identifier:

0x1VMIDOPT is implemented.
CCSIZE, [28:25]

Size of the cycle counter in bits minus 12:

0x0The cycle counter is 12 bits in length.
DVSIZE, [24:20]

Data value size in bytes:

0x00Data value tracing is not implemented.
DASIZE, [19:15]

Data address size in bytes:

0x00Data address tracing is not implemented.
VMIDSIZE, [14:10]

Virtual Machine ID size:

0x4Maximum of 32-bit Virtual Machine ID size.
CIDSIZE, [9:5]

Context ID size in bytes:

0x4Maximum of 32-bit Context ID size.
IASIZE, [4:0]

Instruction address size in bytes:

0x8Maximum of 64-bit address size.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

The TRCIDR2 can be accessed through the external debug interface, offset 0x1E8.

Non-ConfidentialPDF file icon PDF version100442_0200_00_en
Copyright © 2016–2018 Arm Limited or its affiliates. All rights reserved.