D8.66 TRCSSCSR0, Single-Shot Comparator Status Register 0

The TRCSSCSR0 indicates the status of the single-shot comparator. TRCSSCSR0 is sensitive to instruction addresses.

Bit field descriptions

The TRCSSCSR0 is a 32-bit register

Figure D8-63 TRCSSCSR0 bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.

STATUS, [31]

Single-shot status. This indicates whether any of the selected comparators have matched:

0Match has not occurred.
1Match has occurred at least once.

When programming the ETM trace unit, if TRCSSCCRn.RST is b0, the STATUS bit must be explicitly written to 0 to enable this single-shot comparator control.

RES0, [30:3]
DV, [2]

Data value comparator support:

0Single-shot data value comparisons not supported.
DA, [1]

Data address comparator support:

0Single-shot data address comparisons not supported.
INST, [0]

Instruction address comparator support:

1Single-shot instruction address comparisons supported.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

The TRCSSCSR0 can be accessed through the external debug interface, offset 0x2A0.

Non-ConfidentialPDF file icon PDF version100442_0200_00_en
Copyright © 2016–2018 Arm Limited or its affiliates. All rights reserved.