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The TRCLAR controls access to registers using the memory-mapped interface, when PADDRDBG31 is LOW.
When the software lock is set, write accesses using the memory-mapped interface to all ETM trace unit registers are ignored, except for write accesses to the TRCLAR.
When the software lock is set, read accesses of TRCPDSR do not change the TRCPDSR.STICKYPD bit. Read accesses of all other registers are not affected.
The TRCLAR is a 32-bit register.
Software lock key value:
|Clear the software lock.|
All other write values set the software lock.
Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.
The TRCLAR can be accessed through the external debug interface, offset