D8.23 TRCDEVARCH, Device Architecture Register

The TRCDEVARCH identifies the ETM trace unit as an ETMv4 component.

Bit field descriptions

The TRCDEVARCH is a 32-bit register.

Figure D8-21 TRCDEVARCH bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.

ARCHITECT, [31:21]

Defines the architect of the component:

0x4Arm JEP continuation.
0x3BArm JEP 106 code.

Indicates the presence of this register:

0b1Register is present.
REVISION, [19:16]

Architecture revision:

0x02Architecture revision 2.
ARCHID, [15:0]

Architecture ID:

0x4A13ETMv4 component.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

The TRCDEVARCH can be accessed through the external debug interface, offset 0xFBC.

Non-ConfidentialPDF file icon PDF version100442_0200_00_en
Copyright © 2016–2018 Arm Limited or its affiliates. All rights reserved.