A6.6.6 IPA cache descriptor fields

The IPA cache holds mappings from intermediate physical addresses (IPA) to physical addresses. It is only used for translations performed in non-secure EL0/1. It is updated whenever a stage 2 translation is completed, and checked whenever a stage 2 translation is required.

The following table shows the data and tag fields in the IPA cache descriptor.

Table A6-14 IPA cache descriptor fields for Tag RAM

Fields Bits Width Descriptor
Valid [0] 1 Indicates that the entry is valid.
Entry granule [2:1] 2 Indicates the entry granule size.
Unused [4:3] 2 Must be set to 0.
Size [8:5] 4 Indicates the S2 page size for this entry.
DBM [9] 1 Indicates the DBM.
Unused [17:10] 8 Must be set to 0.
VMID [33:18] 16 Indicates the virtual machine identifier.
IPA [57:34] 24

Unused lower bits, page size dependant, must be set to zero.

Unused [79:59] 22 Must be set to zero.
Parity [81:80] 2 If parity is not configured, this bit is absent.

Table A6-15 IPA cache descriptor fields for Data RAM

Fields Bits Width Descriptor
SH [1:0] 2 Shareability.
S2AP [3:2 2 Stage 2 access permissions
XN [5:4] 2 Controls EL1 and EL0 access permissions.
Memattrs [9:6] 4 Stage 2 memory attributes.
PA [37:10] 28 Physical Address.
Unused [42:38] 5 Must be set to zero.
Parity [43] 1 If parity is not configured, this bit is absent.
Non-ConfidentialPDF file icon PDF version100442_0200_00_en
Copyright © 2016–2018 Arm Limited or its affiliates. All rights reserved.