A6.6 Direct access to internal memory

The Cortex®-A55 core provides a mechanism to read the internal memory that is used by the L1 cache and TLB structures through implementation defined system registers. This functionality can be useful when investigating issues where the coherency between the data in the cache and data in system memory is broken.

When the core executes in AArch64 state, the appropriate memory block and location are selected using several write-only registers. The data is read from read-only registers as shown in the following table. These operations are available only in EL3. In all other modes, executing these instructions results in an Undefined Instruction exception.

Table A6-1 AArch64 registers used to access internal memory

Register name Function Access Operation Rd Data
CDBGDR0_EL3 Data Register 0 Read-only MRS <Xd>, S3_6_c15_c0_0 Data
CDBGDR1_EL3 Data Register 1 Read-only MRS <Xd>, S3_6_c15_c0_1 Data
CDBGDR2_EL3 Data Register 2 Read-only MRS <Xd>, S3_6_c15_c0_2 Data
CDBGDCT_EL3 Data Cache Tag Read Operation Register Write-only MSR S1_6_c15_c2_0, <Xd> Set/Way
CDBGICT_EL3 Instruction Cache Tag Read Operation Register Write-only MSR S1_6_c15_c2_1, <Xd> Set/Way
CDBGTT_EL3 TLB Tag Read Operation Register Write-only MSR S1_6_c15_c2_2, <Xd> Index/Way
CDBGDCD_EL3 Data Cache Data Read Operation Register Write-only MSR S1_6_c15_c4_0, <Xd> Set/Way/Offset
CDBGICD_EL3 Instruction Cache Data Read Operation Register Write-only MSR S1_6_c15_c4_1, <Xd> Set/Way/Offset
CDBGTD_EL3 TLB Data Read Operation Register Write-only MSR S1_6_c15_c4_2, <Xd> Index/Way

When the core executes in AArch32 state, the appropriate memory block and location are selected using several write-only system registers. The data is read from read-only system registers as shown in the following table. These operations are available only in EL3. In all other modes, executing the system operation results in an Undefined Instruction exception.

Table A6-2 AArch32 CP15 registers used to access internal memory

Register name Function Access CP15 operation Rd Data
CDBGDR0 Data Register 0 Read-only MRC p15, 6, <Rd>, c15, c0, 0 Data
CDBGDR1 Data Register 1 Read-only MRC p15, 6, <Rd>, c15, c0, 1 Data
CDBGDR2 Data Register 2 Read-only MRC p15, 6, <Rd>, c15, c0, 2 Data
CDBGDCT Data Cache Tag Read Operation Register Write-only MCR p15, 6, <Rd>, c15, c2, 0 Set/Way
CDBGICT Instruction Cache Tag Read Operation Register Write-only MCR p15, 6, <Rd>, c15, c2, 1 Set/Way
CDBGTT TLB Tag Read Operation Register Write-only MCR p15, 6, <Rd>, c15, c2, 2 Index/Way
CDBGDCD Data Cache Data Read Operation Register Write-only MCR p15, 6, <Rd>, c15, c4, 0 Set/Way/Offset
CDBGICD Instruction Cache Data Read Operation Register Write-only MCR p15, 6, <Rd>, c15, c4, 1 Set/Way/Offset
CDBGTD TLB Data Read Operation Register Write-only MCR p15, 6, <Rd>, c15, c4, 2 Index/Way
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