B1.84 TTBCR2, Translation Table Base Control Register 2

The TTBCR2 indicates the hierarchical permission disable and the page based hardware attributes.

Bit field descriptions

TTBCR2 is a 32-bit register, and is part of the Virtual memory control registers functional group.

Figure B1-74 TTBCR2 bit assignments
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RES0, [31:19]
res0Reserved.
HWU162, [18]

Indicates implementation defined hardware use of bit[62] of the stage1 translation table block or level 3 entry. The possible values are:

0

The associated stage 1 translation table entry bit cannot be interpreted by hardware for an implementation defined purpose.

1

The associated stage 1 translation table entry bit can be interpreted by hardware for an implementation defined purpose if the associated TTBCR2.HPD1 ==1.

HWU161, [17]

Indicates implementation defined hardware use of bit[61] of the stage1 translation table block or level 3 entry. The possible values are:

0

The associated stage 1 translation table entry bit cannot be interpreted by hardware for an implementation defined purpose.

1

The associated stage 1 translation table entry bit can be interpreted by hardware for an implementation defined purpose if the associated TTBCR2.HPD1 ==1.

HWU160, [16]

Indicates implementation defined hardware use of bit[60] of the stage1 translation table block or level 3 entry. The possible values are:

0

The associated stage 1 translation table entry bit cannot be interpreted by hardware for an implementation defined purpose.

1

The associated stage 1 translation table entry bit can be interpreted by hardware for an implementation defined purpose if the associated TTBCR2.HPD1 ==1.

HWU159, [15]

Indicates implementation defined hardware use of bit[59] of the stage1 translation table block or level 3 entry. The possible values are:

0

The associated stage 1 translation table entry bit cannot be interpreted by hardware for an implementation defined purpose.

1

The associated stage 1 translation table entry bit can be interpreted by hardware for an implementation defined purpose if the associated TTBCR2.HPD1 ==1.

HWU062, [14]

Indicates implementation defined hardware use of bit[62] of the stage1 translation table block or level 3 entry. The possible values are:

0

The associated stage 1 translation table entry bit cannot be interpreted by hardware for an implementation defined purpose.

1

The associated stage 1 translation table entry bit can be interpreted by hardware for an implementation defined purpose if the associated TTBCR2.HPD0 ==1.

HWU061, [13]

Indicates implementation defined hardware use of bit[61] of the stage1 translation table block or level 3 entry. The possible values are:

0

The associated stage 1 translation table entry bit cannot be interpreted by hardware for an implementation defined purpose.

1

The associated stage 1 translation table entry bit can be interpreted by hardware for an implementation defined purpose if the associated TTBCR2.HPD0 ==1.

HWU060, [12]

Indicates implementation defined hardware use of bit[60] of the stage1 translation table block or level 3 entry. The possible values are:

0

The associated stage 1 translation table entry bit cannot be interpreted by hardware for an implementation defined purpose.

1

The associated stage 1 translation table entry bit can be interpreted by hardware for an implementation defined purpose if the associated TTBCR2.HPD0 ==1.

HWU059, [11]

Indicates implementation defined hardware use of bit[59] of the stage1 translation table block or level 3 entry. The possible values are:

0

The associated stage 1 translation table entry bit cannot be interpreted by hardware for an implementation defined purpose.

1

The associated stage 1 translation table entry bit can be interpreted by hardware for an implementation defined purpose if the associated TTBCR2.HPD0 ==1.

HPD1, [10]
Hierarchical permission disable 1. The possible values are:
0Hierarchical permissions for the TTBR1 region are enabled.
1Hierarchical permissions for the TTBR1 region are disabled if TTBCR.T2E is set to 1. If TTBCR.T2E is set to 0, hierarchical permissions are enabled.
HPD0, [9]
Hierarchical permission disable 0. The possible values are:
0Hierarchical permissions for the TTBR0 region are enabled.
1Hierarchical permissions for the TTBR0 region are disabled if TTBCR.T2E is set to 1. If TTBCR.T2E is set to 0, hierarchical permissions are enabled.
RES0, [8:0]
res0Reserved.
Configurations

TTBCR2 (NS) is architecturally mapped to AArch64 register TCR_EL1. See B2.97 TCR_EL1, Translation Control Register, EL1.

If EL3 is using AArch32, there are separate Secure and Non-secure instances of this register.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

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