B1.29 DISR, Deferred Interrupt Status Register

DISR records that an SError interrupt has been consumed by an ESB instruction.

Bit field descriptions

DISR is a 32-bit register, and is part of the RAS registers group.

There are three formats for this register. The current translation table format determines which format of the register is used.

Configurations

AArch32 register DISR is architecturally mapped to AArch64 register DISR_EL1. See B2.39 DISR_EL1, Deferred Interrupt Status Register, EL1.

There is one instance of DISR that is used in both Secure and Non-secure states.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

This section contains the following subsections:
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