B1.88 VDISR, Virtual Deferred Interrupt Status Register

The VDISR records that a virtual SError interrupt has been consumed by an ESB instruction executed at Non-secure EL1.

Bit field descriptions

VDISR is a 32-bit register, and is part of Reliability, Availability, Serviceability (RAS) registers functional group.

There are two formats for this register. The current translation table format determines which format of the register is used:

Configurations

There is one instance of VDISR that is used in both Secure and Non-secure states.

Present only if all of the following are present and is UNDEFINED otherwise:

  • EL2 is implemented and using AArch32.
  • The RAS extension is implemented.

If the highest implemented Exception level is using AArch64, AArch32 System register VDISR is architecturally mapped to AArch64 System register VDISR_EL2. See B2.105 VDISR_EL2, Virtual Deferred Interrupt Status Register, EL2.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

This section contains the following subsections:
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