B1.40 ERXMISC2, Selected Error Record Miscellaneous Register 2

Register ERXMISC2 accesses bits [31:0] of the ERR<n>MISC1 miscellaneous register 1 for the error record selected by ERRSELR.SEL.

If ERRSELR.SEL==0, then ERXMISC2 accesses the ERR0MISC1[31:0] register of the core error record. See B3.6 ERR0MISC1, Error Record Miscellaneous Register 1.

If ERRSELR.SEL==1, then ERXMISC2 accesses the ERR1MISC1[31:0] register of the DSU error record. See the Arm® DynamIQ™ Shared Unit Technical Reference Manual.

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