B2.105 VDISR_EL2, Virtual Deferred Interrupt Status Register, EL2

The VDISR_EL2 records that a virtual SError interrupt has been consumed by an ESB instruction executed at Non-secure EL1.

Bit field descriptions

VDISR_EL2 is a 64-bit register, and is part of the Reliability, Availability, Serviceability (RAS) registers functional group.

There are three formats for this register. The current translation table format determines which format of the register is used.


VDISR_EL2 is res0 at EL3 if EL2 is not implemented.

Present only if all the following are present and is UNDEFINED otherwise.

If the implementation supports AArch32 at EL2, VDISR_EL2 is architecturally mapped to VDISR. See B1.88 VDISR, Virtual Deferred Interrupt Status Register.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

This section contains the following subsections:
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