B2.39 DISR_EL1, Deferred Interrupt Status Register, EL1

The DISR_EL1 records the SError interrupts consumed by an ESB instruction.

Bit field descriptions

DISR_EL1 is a 64-bit register, and is part of the registers Reliability, Availability, Serviceability (RAS) functional group.

Figure B2-34 DISR_EL1 bit assignments, DISR_EL1.IDS is 0
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RES0, [63:32]
Reserved, RES0.
A, [31]

Set to 1 when ESB defers an asynchronous SError interrupt. If the implementation does not include any synchronizable sources of SError interrupt, this bit is res0.

RES0, [30:25]
Reserved, RES0.
IDS, [24]

Indicates the type of format the deferred SError interrupt uses. The value of this bit is:


Deferred error uses architecturally-defined format.

RES0, [23:13]
Reserved, RES0.
AET, [12:10]

Asynchronous Error Type. Describes the state of the core after taking an asynchronous Data Abort exception. The value or values are:

0b001Unrecoverable error (UEU).

All other values are reserved. Reserved values might be defined in a future version of the architecture.

In the event of multiple errors taken as a single SError interrupt exception, the overall state of the PE is reported. For example, if both a Recoverable and Unrecoverable error occurred, the state is Unrecoverable.


  • This field is only valid if IDS == 0b0 and DFSC == 0b010001.
  • The recovery software must also examine any implemented fault records to determine the location and extent of the error.
RES0, [9:6]
Reserved, RES0.
DFSC, [5:0]

Data Fault Status Code. The possible values are:


Asynchronous SError Interrupt when the core is executing in AArch64 state or at EL2, or when the core is executing in AArch32 state at EL1, and the Extended Address Enable bit is at 1 in TTBCR.


Asynchronous SError Interrupt when the core is executing in AArch32 state at EL1 and the Extended Address Enable is at 0 in TTBCR.


AArch64 System register DISR_EL1 is architecturally mapped to AArch32 register DISR. See B1.29 DISR, Deferred Interrupt Status Register.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

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