B1.2 AArch32 architectural system register summary

This section identifies the AArch32 architectural system registers implemented in the Cortex®-A55 core.

The section contains two tables:

Registers with implementation defined bit fields

This table identifies the architecturally defined registers in the Cortex-A55 core that have implementation defined bit fields. The register descriptions for these registers only contain information about the implementation defined features.

See Table   B1-1 Registers with implementation defined bit fields.

Other architecturally defined registers

This table identifies the other architecturally defined registers that are implemented in the Cortex-A55 core. These registers are described in the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

See Table   B1-2 Other architecturally defined registers.

Registers with implementation defined bit fields

For all the registers listed in the following table, coproc==0b1111.

Table B1-1 Registers with implementation defined bit fields

Name CRn Opc1 CRm Opc2 Width Description
ACTLR c1 0 c0 1 32 B1.5 ACTLR, Auxiliary Control Register
ACTLR2 c1 0 c0 3 32 B1.6 ACTLR2, Auxiliary Control Register 2
AIDR c0 1 c0 7 32 B1.9 AIDR, Auxiliary ID Register
ADFSR c5 0 c1 0 32 B1.7 ADFSR, Auxiliary Data Fault Status Register
AIFSR c5 0 c1 1 32 B1.10 AIFSR, Auxiliary Instruction Fault Status Register
AMAIR0 c10 0 c3 0 32 B1.11 AMAIR0, Auxiliary Memory Attribute Indirection Register 0
AMAIR1 c10 0 c3 1 32 B1.12 AMAIR1, Auxiliary Memory Attribute Indirection Register 1
CCSIDR c0 1 c0 0 32 B1.15 CCSIDR, Cache Size ID Register
CLIDR c0 1 c0 1 32 B1.16 CLIDR, Cache Level ID Register
CPACR c1 0 c0 2 32 B1.17 CPACR, Architectural Feature Access Control Register
CSSELR c0 2 c0 0 32 B1.26 CSSELR, Cache Size Selection Register
CTR c0 0 c0 1 32 B1.27 CTR, Cache Type Register
DFSR c5 0 c0 0 32 B1.28 DFSR, Data Fault Status Register
DISR c12 0 c1 1 32 B1.29 DISR, Deferred Interrupt Status Register
ERRIDR c5 0 c3 0 32 B1.30 ERRIDR, Error ID Register
ERRSELR c5 0 c3 1 32 B1.31 ERRSELR, Error Record Select Register
ERXADDR c5 0 c4 3 32 B1.32 ERXADDR, Selected Error Record Address Register
ERXADDR2 c5 0 c4 7 32 B1.33 ERXADDR2, Selected Error Record Address Register 2
ERXCTLR c5 0 c4 1 32 B1.34 ERXCTLR, Selected Error Record Control Register
ERXCTLR2 c5 0 c4 5 32 B1.35 ERXCTLR2, Selected Error Record Control Register 2
ERXFR c5 0 c4 0 32 B1.36 ERXFR, Selected Error Record Feature Register
ERXFR2 c5 0 c4 4 32 B1.37 ERXFR2, Selected Error Record Feature Register 2
ERXMISC0 c5 0 c5 0 32 B1.38 ERXMISC0, Selected Error Miscellaneous Register 0
ERXMISC1 c5 0 c5 1 32 B1.39 ERXMISC1, Selected Error Miscellaneous Register 1
ERXMISC2 c5 0 c5 4 32 B1.40 ERXMISC2, Selected Error Record Miscellaneous Register 2
ERXMISC3 c5 0 c5 5 32 B1.41 ERXMISC3, Selected Error Record Miscellaneous Register 3
ERXSTATUS c5 0 c4 2 32 B1.45 ERXSTATUS, Selected Error Record Primary Status Register
FCSEIDR c13 0 c0 0 32 B1.46 FCSEIDR, FCSE Process ID Register
FPSID c5 4 c3 1 32

Floating-Point System ID Register. For more information, see the Arm® Cortex®-A55 Core Advanced SIMD and Floating-point Support Technical Reference Manual.

HACR c1 4 c1 7 32 B1.47 HACR, Hyp Auxiliary Configuration Register
HACTLR c1 4 c0 1 32 B1.48 HACTLR, Hyp Auxiliary Control Register
HACTLR2 c1 4 c0 3 32 B1.49 HACTLR2, Hyp Auxiliary Control Register 2
HADFSR c5 4 c1 0 32 B1.50 HADFSR, Hyp Auxiliary Data Fault Status Syndrome Register
HAIFSR c5 4 c1 1 32 B1.51 HAIFSR, Hyp Auxiliary Instruction Fault Status Syndrome Register
HAMAIR0 c10 4 c3 0 32 B1.52 HAMAIR0, Hyp Auxiliary Memory Attribute Indirection Register 0
HAMAIR1 c10 4 c3 1 32 B1.53 HAMAIR1, Hyp Auxiliary Memory Attribute Indirection Register 1
HCR c1 4 c1 0 32 B1.54 HCR, Hyp Configuration Register
HCR2 c1 4 c1 4 32

B1.55 HCR2, Hyp Configuration Register 2

HSR c5 4 c2 0 32 B1.57 HSR, Hyp Syndrome Register
ID_AFR0 c0 0 c1 3 32 B1.59 ID_AFR0, Auxiliary Feature Register 0
ID_DFR0 c0 0 c1 2 32 B1.60 ID_DFR0, Debug Feature Register 0
ID_ISAR0 c0 0 c2 0 32 B1.61 ID_ISAR0, Instruction Set Attribute Register 0
ID_ISAR1 c0 0 c2 1 32 B1.62 ID_ISAR1, Instruction Set Attribute Register 1
ID_ISAR2 c0 0 c2 2 32 B1.63 ID_ISAR2, Instruction Set Attribute Register 2
ID_ISAR3 c0 0 c2 3 32 B1.64 ID_ISAR3, Instruction Set Attribute Register 3
ID_ISAR4 c0 0 c2 4 32 B1.65 ID_ISAR4, Instruction Set Attribute Register 4
ID_ISAR5 c0 0 c2 5 32 B1.66 ID_ISAR5, Instruction Set Attribute Register 5
ID_ISAR6 c0 0 c2 7 32 B1.67 ID_ISAR6, Instruction Set Attribute Register 6
ID_MMFR0 c0 0 c1 4 32 B1.68 ID_MMFR0, Memory Model Feature Register 0
ID_MMFR1 c0 0 c1 5 32 B1.69 ID_MMFR1, Memory Model Feature Register 1
ID_MMFR2 c0 0 c1 6 32 B1.70 ID_MMFR2, Memory Model Feature Register 2
ID_MMFR3 c0 0 c1 7 32 B1.71 ID_MMFR3, Memory Model Feature Register 3
ID_MMFR4 c0 0 c2 6 32 B1.72 ID_MMFR4, Memory Model Feature Register 4
ID_PFR0 c0 0 c1 0 32 B1.73 ID_PFR0, Processor Feature Register 0
ID_PFR1 c0 0 c1 1 32 B1.74 ID_PFR1, Processor Feature Register 1
IFSR c5 0 c0 1 32 B1.75 IFSR, Instruction Fault Status Register
MIDR c0 0 c0 0, 4, or 7 32 B1.76 MIDR, Main ID Register
MPIDR c0 0 c0 5 32 B1.77 MPIDR, Multiprocessor Affinity Register
PAR (32 bits access) c7 0 c4 0 32 B1.78 PAR, Physical Address Register
PAR (64 bits access) - 0 c7 - 64 B1.78 PAR, Physical Address Register
REVIDR c0 0 c0 6 32 B1.79 REVIDR, Revision ID Register
SCR c1 0 c1 0 32 B1.80 SCR, Secure Configuration Register
SCTLR c1 0 c0 0 32 B1.81 SCTLR, System Control Register
SDCR c1 0 c3 1 32 B1.82 SDCR, Secure Debug Control Register
TTBCR c2 0 c0 2 32 B1.83 TTBCR, Translation Table Base Control Register
TTBR0 (32 bits access) c2 0 c0 0 32 B1.85 TTBR0, Translation Table Base Register 0
TTBR0 (64 bits access) - 0 c2 - 64 B1.85 TTBR0, Translation Table Base Register 0
TTBR1 (32 bits access) c2 0 c0 1 32 B1.86 TTBR1, Translation Table Base Register 1
TTBR1 (64 bits access) - 1 c2 - 64 B1.86 TTBR1, Translation Table Base Register 1
VDFSR c5 4 c2 3 32 B1.87 VDFSR, Virtual SError Exception Syndrome Register
VDISR c12 4 c1 1 32 B1.88 VDISR, Virtual Deferred Interrupt Status Register
VMPIDR c0 4 c0 5 32 B1.89 VMPIDR, Virtualization Multiprocessor ID Register
VPIDR c0 4 c0 0 32 B1.90 VPIDR, Virtualization Processor ID Register
VTCR c2 4 c1 2 32 B1.91 VTCR, Virtualization Translation Control Register
VTTBR - 6 c2 - 64 B1.92 VTTBR, Virtualization Translation Table Base Register

Other architecturally defined registers

For the registers listed in the following table, coproc==0b1111, except for:

  • Jazelle ID Register.
  • Jazelle Main Configuration Register.
  • Jazelle OS Control Register.

For these registers, coproc==0b1110.

Table B1-2 Other architecturally defined registers

Name CRn Opc1 CRm Opc2 Width description
CPACR c1 0 c0 2 32 Architectural Feature Access Control Register
CNTFRQ c14 0 c0 0 32 Timer Clock Ticks per Second
CNTHCTL c14 4 c1 0 32 Timer Hyp Control register
CNTHP_CTL c14 4 c2 1 32 Counter-timer Hyp Physical Timer Control register
CNTHP_CVAL - 6 c14 - 64 Counter-timer Hyp Physical CompareValue register
CNTHP_TVAL c14 4 c2 0 32 Counter-timer Hyp Physical Timer TimerValue register
CNTKCTL c14 0 c1 0 32 Counter-timer Kernel Control register
CNTP_CTL c14 0 c2 1 32 Counter-timer Physical Timer Control register
CNTP_CVAL - 2 c14 - 64 Counter-timer Physical Timer CompareValue register
CNTP_TVAL c14 0 c2 0 32 Counter-timer Physical Timer TimerValue register
CNTPCT - 0 c14 - 64 Counter-timer Physical Count register
CNTV_CTL c14 0 c3 1 32 Counter-timer Virtual Timer Control register
CNTV_CVAL - 3 c14 - 64 Counter-timer Virtual Timer CompareValue register
CNTV_TVAL c14 0 c3 0 32 Counter-timer Virtual Timer TimerValue register
CNTVCT - 1 c14 - 64 Counter-timer Virtual Count register
CNTVOFF - 4 c14 - 64 Counter-timer Virtual Offset register
CONTEXTIDR c13 0 c0 1 32 Context ID Register
DACR c3 0 c0 0 32 Domain Access Control Register
DFAR c6 0 c0 0 32 Data Fault Address Register
DLR c4 3 c5 1 32 Debug Link Register
DSPSR c4 3 c5 0 32 Debug Saved Program Status Register
FPEXC c5 4 c3 0 32 Floating-point Exception Control register
HCPTR c1 4 c1 2 32 Hypervisor Coprocessor Trap Register
HDCR c1 4 c1 1 32 Hypervisor Debug Control Register
HDFAR c6 4 c0 0 32 Hypervisor Data Fault Address
HIFAR c6 4 c0 2 32 Hypervisor Instruction Fault Address
HMAIR0 c10 4 c2 0 32 Hypervisor Memory Attribute Indirection Register 0
HMAIR1 c10 4 c2 1 32 Hypervisor Memory Attribute Indirection Register 1
HPFAR c6 4 c0 4 32 Hypervisor IPA Fault Address
HTCR c2 4 c0 2 32 Hypervisor Translation Control Register
HTPIDR c13 4 c0 2 32 Hypervisor Software Thread ID Register
HTTBR - 4 c2 - 64 Hypervisor Translation Table Base Register
HVBAR c12 4 c0 0 32 Hypervisor Vector Base Address
IFAR c6 0 c0 2 32 Instruction Fault Address Register
ISR c12 0 c1 0 32 Interrupt Status Register
JIDR c0 7 c0 0 32 Jazelle ID Register
JMCR c2 7 c0 0 32 Jazelle Main Configuration Register
JOSCR c1 7 c0 0 32 Jazelle OS Control Register
MAIR0 c10 0 c2 1 32 Memory Attribute Indirection Register 0
MAIR1 c10 0 c2 1 32 Memory Attribute Indirection Register 1
MVBAR c12 0 c0 1 32 Monitor Vector Base Address Register
MVFR0 c0 2 c3 0 32 Media and VFP Feature Register 0
MVFR1 c0 2 c3 1 32 Media and VFP Feature Register 1
MVFR2 c0 2 c3 2 32 Media and VFP Feature Register 2
NMRR c10 0 c2 1 32 Normal Memory Remap Register
PRRR c10 0 c2 0 32 Primary Region Remap Register
RMR c12 0 c0 2 32 Reset Management Register
SDER c1 0 c1 1 32 Secure Debug Enable Register
TCMTR c0 0 c0 2 32 TCM Type Register
TLBTR c0 0 c0 3 32 TLB Type Register
TPIDRPRW c13 0 c0 4 32 Privileged Only Thread ID Register
TPIDRURO c13 0 c0 3 32 User Read Only Thread ID Register
TPIDRURW c13 0 c0 2 32 User Read/Write Thread ID Register
VBAR c12 0 c0 0 32 Vector Base Address Register
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