B1.3 AArch32 implementation defined register summary

This section identifies the AArch32 registers implemented in the Cortex®-A55 core that are implementation defined. The list of registers is sorted by opcode.

The registers that are implemented but are architecturally defined are described in the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

Table B1-3 Cortex-A55 AArch32 implementation defined registers

Name Copro CRn Opc1 CRm Opc2 Width Description
AHTCR cp15 c15 4 c7 0 32 B1.8 AHTCR, Auxiliary Hypervisor Translation Control Register
ATTBCR cp15 c15 0 c7 1 32 B1.13 ATTBCR, Auxiliary Translation Table Base Control Register
AVTCR cp15 c15 4 c7 1 32 B1.14 AVTCR, Auxiliary Virtualized Translation Control Register
CPUACTLR cp15 - 0 c15 - 64 B1.18 CPUACTLR, CPU Auxiliary Control Register
CPUCFR cp15 c15 0 c0 0 32 B1.19 CPUCFR, CPU Configuration Register
CPUECTLR cp15 - 4 c15 - 64 B1.20 CPUECTLR, CPU Extended Control Register
CPUPCR cp15 c15 6 c8 1 64 B1.21 CPUPCR, CPU Private Control Register
CPUPMR cp15 c15 6 c8 3 64 B1.22 CPUPMR, CPU Private Mask Register
CPUPOR cp15 c15 6 c8 2 64 B1.23 CPUPOR, CPU Private Operation Register
CPUPSELR cp15 c15 6 c8 0 32 B1.24 CPUPSELR, CPU Private Selection Register
CPUPWRCTLR cp15 c15 0 c2 7 32 B1.25 CPUPWRCTLR, CPU Power Control Register
ERR0PFGFRa N/A N/A N/A N/A N/A 32 B3.9 ERR0PFGFR, Error Pseudo Fault Generation Feature Register
ERR0PFGCTLRa N/A N/A N/A N/A N/A 32 B3.8 ERR0PFGCTLR, Error Pseudo Fault Generation Control Register
ERR0PFGCDNRa N/A N/A N/A N/A N/A 32 B3.7 ERR0PFGCDNR, Error Pseudo Fault Generation Count Down Register
ERXPFGCDNR cp15 c15 0 c2 2 32 B1.42 ERXPFGCDNR, Selected Error Pseudo Fault Generation Count Down Register
ERXPFGCTLR cp15 c15 0 c2 1 32 B1.43 ERXPFGCTLR, Selected Error Pseudo Fault Generation Control Register
ERXPFGFR cp15 c15 0 c2 0 32 B1.44 ERXPFGFR, Selected Pseudo Fault Generation Feature Register

The following table shows the 32-bit wide implementation defined Cluster registers. Details of these registers can be found in Arm® DynamIQ™ Shared Unit Technical Reference Manual

Table B1-4 Cluster registers

Name Copro CRn Opc1 CRm Opc2 Width Description
CLUSTERCFR cp15 c15 0 c3 0 32-bit Cluster configuration register.
CLUSTERIDR cp15 c15 0 c3 1 32-bit Cluster main revision ID.
CLUSTEREVIDR cp15 c15 0 c3 2 32-bit Cluster ECO ID.
CLUSTERACTLR cp15 c15 0 c3 3 32-bit Cluster auxiliary control register.
CLUSTERECTLR cp15 c15 0 c3 4 32-bit Cluster extended control register.
CLUSTERPWRCTLR cp15 c15 0 c3 5 32-bit Cluster power control register.
CLUSTERPWRDN cp15 c15 0 c3 6 32-bit Cluster power down register.
CLUSTERPWRSTAT cp15 c15 0 c3 7 32-bit Cluster power status register.
CLUSTERTHREADSID cp15 c15 0 c4 0 32-bit Cluster thread scheme ID register.
CLUSTERACPSID cp15 c15 0 c4 1 32-bit Cluster ACP scheme ID register.
CLUSTERSTASHSID cp15 c15 0 c4 2 32-bit Cluster stash scheme ID register.
CLUSTERPARTCR cp15 c15 0 c4 3 32-bit Cluster partition control register.
CLUSTERBUSQOS cp15 c15 0 c4 4 32-bit Cluster bus QoS control register.
CLUSTERL3HIT cp15 c15 0 c4 5 32-bit Cluster L3 hit counter register.
CLUSTERL3MISS cp15 c15 0 c4 6 32-bit Cluster L3 miss counter register.
CLUSTERTHREADSIDOVR cp15 c15 0 c4 7 32-bit Cluster thread scheme ID override register.
CLUSTERPM* cp15 c15 0 or 6 c5-c6 0-7 32-bit or 64-bit Cluster PMU registers.
a There is no direct access to ERR0* registers using MCR and MRC.
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