B1.29.3 DISR at EL2

DISR has a specific format when written at EL2.

The following figure shows the DISR bit assignments when written at EL2:

Figure B1-28 DISR bit assignments for Long-descriptor translation table format
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A, [31]

Set to 1 when ESB defers an asynchronous SError interrupt. If the implementation does not include any synchronizable sources of SError interrupt, this bit is res0.

RES0, [30:12]
res0 Reserved.
AET, [11:10]

Asynchronous Error Type. Describes the state of the core after taking the SError interrupt exception. Software might use the information in the syndrome registers to determine what recovery might be possible. The value is:

0b01

Uncorrected error, Unrecoverable error (UEU).

EA, [9]

External Abort Type. This bit is defined as RES0.

RES0, [8:6]
res0Reserved.
DFSC, [5:0]

Fault Status Code. This field indicates the type of exception generated. See the description of HSR.DFSC in the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile for an SError interrupt.

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