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VTTBR holds the base address of the translation table for the stage 2 translation of memory accesses from Non-secure modes other than Hyp mode.
VTTBR is a 64-bit register, and is part of:
CnP is not supported.
VTTBR is architecturally mapped to AArch64 register VTTBR_EL1. See B2.110 VTTBR_EL2, Virtualization Translation Table Base Register, EL2.
This register is used with the VTCR.
Some or all RW fields of this register have defined reset values. These apply only if the core resets into EL2 with EL2 using AArch32, or into EL3 with EL3 using AArch32. Otherwise, RW fields in this register reset to architecturally UNKNOWN values.
Bit fields and details that are not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.