B4.9 ICC_MCTLR, Interrupt Controller Monitor Control Register

ICC_MCTLR controls aspects of the behavior of the GIC CPU interface and provides information about the features implemented.

Bit field descriptions

ICC_MCTLR is a 32-bit register and is part of:

  • The GIC system registers functional group.
  • The Security registers functional group.
  • The GIC control registers functional group.
Figure B4-5 ICC_MCTLR bit assignments
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RES0, [31:18]
Reserved, RES0.
nDS, [17]

Disable Security not supported. Read-only and writes are ignored. The value is:

0x1

The CPU interface logic does not support disabling of security, and requires that security is not disabled.

RES0, [16]
Reserved, RES0.
A3V, [15]

Affinity 3 Valid. The value is:

0x1

The CPU interface logic supports non-zero values of the Aff3 field in SGI generation System registers.

SEIS, [14]

SEI Support. The value is:

0x0

The CPU interface logic does not support generation of SEIs.

IDbits, [13:11]

Identifier bits. The value is:

0x0The number of physical interrupt identifier bits supported is 16 bits.

This field is an alias of ICC_CTLR_EL3.IDbits.

PRIbits, [10:8]

Priority bits. The value is:

0x4The core support 32 levels of physical priority with 5 priority bits.
RES0, [7]
Reserved, RES0.
PMHE, [6]
Priority Mask Hint Enable.
RM, [5]

SBZ. The equivalent bit in AArch64 is the Routing Modifier bit. This feature is not supported when EL3 is using AArch32. The value is:

0x0
EOImode_EL1NS, [4]

EOI mode for interrupts handled at Non-secure EL1 and EL2. Controls whether a write to an End of Interrupt register also deactivates the interrupt.

EOI mode for interrupts handled at Non-secure EL1 and EL2.

EOImode_EL1S, [3]

EOI mode for interrupts handled at Secure EL1. Controls whether a write to an End of Interrupt register also deactivates the interrupt.

EOI mode for interrupts handled at Secure EL1

EOImode_EL3, [2]

EOI mode for interrupts handled at EL3. Controls whether a write to an End of Interrupt register also deactivates the interrupt.

EOI mode for interrupts handled at EL3.

CBPR_EL1NS, [1]

Common Binary Point Register, EL1 Non-secure.

Control whether the same register is used for interrupt pre-emption of both Group 0 and Group 1 Non-secure interrupts at EL1 and EL2.

CBPR_EL1S, [0]

Common Binary Point Register, EL1 Secure.

Control whether the same register is used for interrupt pre-emption of both Group 0 and Group 1 Secure interrupt at EL1.

Configurations

This register is only accessible in Secure state.

AArch32 System register ICC_MCTLR can be mapped to AArch64 System register ICC_CTLR_EL3.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Generic Interrupt Controller Architecture Specification.

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