B4.21 ICH_HCR, Interrupt Controller Hyp Control Register

ICH_HCR controls the environment for VMs.

Bit field descriptions

ICH_HCR is a 32-bit register and is part of:

  • The GIC system registers functional group.
  • The Virtualization registers functional group.
  • The GIC host interface control registers functional group.
Figure B4-11 ICH_HCR bit assignments
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EOIcount, [31:27]

Number of outstanding deactivates.

RES0, [26:15]

Reserved, RES0.

TDIR, [14]

Trap Non-secure EL1 writes to ICC_DIR and ICV_DIR. The possible values are:

0x0

Non-secure EL1 writes of ICC_DIR and ICV_DIR are not trapped to EL2, unless trapped by other mechanisms.

0x1Non-secure EL1 writes of ICC_DIR and ICV_DIR are trapped to EL2.
TSEI, [13]

Trap all locally generated SEIs. The value is:

0x0

Locally generated SEIs do not cause a trap to EL2.

TALL1, [12]

Trap all Non-secure EL1 accesses to ICC_* and ICV_* System registers for Group 1 interrupts to EL2. The possible values are:

0x0

Non-Secure EL1 accesses to ICC_* and ICV_* registers for Group 1 interrupts proceed as normal.

0x1

Non-secure EL1 accesses to ICC_* and ICV_* registers for Group 1 interrupts trap to EL2.

TALL0, [11]

Trap all Non-secure EL1 accesses to ICC_* and ICV_* System registers for Group 0 interrupts to EL2. The possible values are:

0x0

Non-Secure EL1 accesses to ICC_* and ICV_* registers for Group 0 interrupts proceed as normal.

0x1

Non-secure EL1 accesses to ICC_* and ICV_* registers for Group 0 interrupts trap to EL2.

TC, [10]

Trap all Non-secure EL1 accesses to System registers that are common to Group 0 and Group 1 to EL2. The possible values are:

0x0

Non-secure EL1 accesses to common registers proceed as normal.

0x1

Non-secure EL1 accesses to common registers trap to EL2.

RES0, [9:8]

Reserved, RES0.

VGrp1DIE, [7]

VM Group 1 Disabled Interrupt Enable. The possible values are:

0x0

Maintenance interrupt disabled.

0x1

Maintenance interrupt signaled when ICH_VMCR.VENG1 is 0.

VGrp1EIE, [6]

VM Group 1 Enabled Interrupt Enable. The possible values are:

0x0

Maintenance interrupt disabled.

0x1

Maintenance interrupt signaled when ICH_VMCR.VENG1 is 1.

VGrp0DIE, [5]

VM Group 0 Disabled Interrupt Enable. The possible values are:

0x0

Maintenance interrupt disabled.

0x1

Maintenance interrupt signaled when ICH_VMCR.VENG0 is 0.

VGrp0EIE, [4]

VM Group 0 Enabled Interrupt Enable. The possible values are:

0x0

Maintenance interrupt disabled.

0x1

Maintenance interrupt signaled when ICH_VMCR.VENG0 is 1.

NPIE, [3]

No Pending Interrupt Enable. The possible values are:

0x0

Maintenance interrupt disabled.

0x1

Maintenance interrupt signaled while the List registers contain no interrupts in the pending state.

LRENPIE, [2]

List Register Entry Not Present Interrupt Enable. The possible values are:

0x0

Maintenance interrupt disabled.

0x1

Maintenance interrupt is asserted while the EOIcount field is not 0.

UIE, [1]

Underflow Interrupt Enable. The possible values are:

0x0

Maintenance interrupt disabled.

0x1

Maintenance interrupt is asserted if none, or only one, of the List register entries is marked as a valid interrupt.

En, [0]
Enable. The possible values are:
0x0

Virtual CPU interface operation disabled.

0x1

Virtual CPU interface operation enabled.

Configurations

AArch32 System register ICH_HSR can be mapped to AArch64 System register ICH_HSR_EL2.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Generic Interrupt Controller Architecture Specification.

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