B4.22 ICH_VMCR, Interrupt Controller Virtual Machine Control Register

ICH_VMCR enables the hypervisor to save and restore the virtual machine view of the GIC state.

Bit field descriptions

ICH_VMCR is a 32-bit register and is part of:

  • The GIC system registers functional group.
  • The Virtualization registers functional group.
  • The GIC host interface control registers functional group.
Figure B4-12 ICH_VMCR bit assignments
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VPMR, [31:24]

Virtual Priority Mask.

This field is an alias of ICV_PMR.Priority.

VBPR0, [23:21]

Virtual Binary Point Register, Group 0. The minimum value is:

0x2

This field is an alias of ICV_BPR0.BinaryPoint.

VBPR1, [20:18]
Virtual Binary Point Register, Group 1. The minimum value is:
0x3

This field is an alias of ICV_BPR1.BinaryPoint.

[17:10]

Reserved, RES0.

VEOIM, [9]

Virtual EOI mode. The possible values are:

0x0

ICV_EOIR0 and ICV_EOIR1 provide both priority drop and interrupt deactivation functionality. Accesses to ICV_DIR are UNPREDICTABLE.

0x1

ICV_EOIR0 and ICV_EOIR1 provide priority drop functionality only. ICV_DIR provides interrupt deactivation functionality.

This bit is an alias of ICV_CTLR.EOImode.

[8:5]

Reserved, RES0.

VCBPR, [4]

Virtual Common Binary Point Register. The possible values are:

0x0

ICV_BPR0 determines the preemption group for virtual Group 0 interrupts only.

ICV_BPR1 determines the preemption group for virtual Group 1 interrupts.

0x1

ICV_BPR0 determines the preemption group for both virtual Group 0 and virtual Group 1 interrupts.

Reads of ICV_BPR1 return ICV_BPR0 plus one, saturated to 111. Writes to ICV_BPR1 are ignored.

VFIQEn, [3]

Virtual FIQ enable. The value is:

0x1

Group 0 virtual interrupts are presented as virtual FIQs.

[2]

Reserved, RES0.

VENG1, [1]

Virtual Group 1 interrupt enable. The possible values are:

0x0

Virtual Group 1 interrupts are disabled.

0x1

Virtual Group 1 interrupts are enabled.

This bit is an alias of ICV_IGRPEN1.Enable.

VENG0, [0]

Virtual Group 0 interrupt enable. The possible values are:

0x0

Virtual Group 0 interrupts are disabled.

0x1

Virtual Group 0 interrupts are enabled.

This bit is an alias of ICV_IGRPEN0.Enable.

Configurations

AArch32 System register ICH_VMCR can be mapped to AArch64 System register ICH_VMCR_EL2.

If EL2 is not implemented, this register is RES0 from EL3.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Generic Interrupt Controller Architecture Specification.

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