B4.17 ICV_CTLR, Interrupt Controller Virtual Control Register

ICV_CTLR controls aspects of the behavior of the GIC virtual CPU interface and provides information about the features implemented.

Bit field descriptions

ICV_CTLR is a 32-bit register and is part of:

  • The GIC system registers functional group.
  • The GIC virtual interface control registers functional group.
Figure B4-10 ICV_CTLR bit assignments
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RES0, [31:16]

Reserved, RES0.

A3V, [15]

Affinity 3 Valid. The value is:

0x1

The virtual CPU interface logic supports non-zero values of Affinity 3 in SGI generation System registers.

SEIS, [14]

SEI Support. The value is:

0x0

The virtual CPU interface logic does not support local generation of SEIs.

IDbits, [13:11]

Identifier bits. The value is:

0x0

The number of physical interrupt identifier bits supported is 16 bits.

PRIbits, [10:8]

Priority bits. The value is:

0x4

Support 32 levels of physical priority (5 priority bits).

RES0, [7:2]

Reserved, RES0.

VEOImode, [1]

Virtual EOI mode. The possible values are:

0x0

ICV_EOIR0 and ICV_EOIR1 provide both priority drop and interrupt deactivation functionality. Accesses to ICV_DIR are unpredictable.

0x1

ICV_EOIR0 and ICV_EOIR1 provide priority drop functionality only. ICV_DIR provides interrupt deactivation functionality.

VCBPR, [0]

Common Binary Point Register. Controls whether the same register is used for interrupt preemption of both virtual Group 0 and virtual Group 1 interrupts. The possible values are:

0

ICV_BPR0 determines the preemption group for virtual Group 0 interrupts only.

ICV_BPR1 determines the preemption group for virtual Group 1 interrupts.

1

ICV_BPR0 determines the preemption group for both virtual Group 0 and virtual Group 1 interrupts.

Reads of ICV_BPR1 return ICV_BPR0 plus one, saturated to 111. Writes to ICV_BPR1 are ignored.

Configurations

AArch32 System register ICV_CTLR is architecturally mapped to AArch64 System register ICV_CTLR_EL1.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Generic Interrupt Controller Architecture Specification.

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