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ICC_SRE_EL3 controls whether the System register interface or the memory-mapped interface to the GIC CPU interface is used for EL3.
ICC_SRE_EL3 is a 32-bit register and is part of:
Enables lower Exception level access to ICC_SRE_EL1 and ICC_SRE_EL2. The value is:
This bit is RAO/WI.
Disable IRQ bypass. The possible values are:
IRQ bypass enabled.
IRQ bypass disabled.
Disable FIQ bypass. The possible values are:
FIQ bypass enabled.
FIQ bypass disabled.
System Register Enable. The value is:
The System register interface for the current Security state is enabled.
This bit is RAO/WI. The core only supports a system register interface to the GIC CPU interface.
AArch64 System register ICC_SRE_EL3 can be mapped to AArch32 System register ICC_MSRE.
Bit fields and details that are not provided in this description are architecturally defined. See the Arm® Generic Interrupt Controller Architecture Specification.