B4.45 ICH_VTR_EL2, Interrupt Controller VGIC Type Register, EL2

ICH_VTR_EL2 reports supported GIC virtualization features.

Bit field descriptions

ICH_VTR_EL2 is a 32-bit register and is part of:

  • The GIC system registers functional group.
  • The Virtualization registers functional group.
  • The GIC host interface control registers functional group.
Figure B4-26 ICH_VTR_EL2 bit assignments
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PRIbits, [31:29]

Priority bits. The number of virtual priority bits implemented, minus one.

0x4

Priority implemented is 5-bit.

PREbits, [28:26]

The number of virtual preemption bits implemented, minus one. The value is:

0x4

Virtual preemption implemented is 5-bit.

IDbits, [25:23]

The number of virtual interrupt identifier bits supported. The value is:

0x0

Virtual interrupt identifier bits that are implemented is 16-bit.

SEIS, [22]

SEI Support. The value is:

0x0

The virtual CPU interface logic does not support generation of SEIs.

A3V, [21]

Affinity 3 Valid. The value is:

0x1

The virtual CPU interface logic supports non-zero values of Affinity 3 in SGI generation System registers.

nV4, [20]

Direct injection of virtual interrupts not supported. The value is:

0x0

The CPU interface logic supports direct injection of virtual interrupts.

TDS, [19]

Separate trapping of Non-secure EL1 writes to ICV_DIR_EL1 supported. The value is:

0x1

Implementation supports ICH_HCR_EL2.TDIR.

RES0, [18:5]
RES0Reserved.
ListRegs, [4:0]
0x3

The number of implemented List registers, minus one.

The core implements 4 list registers. Accesses to ICH_LR_EL2[x] (x>3) in AArch64 or ICH_LR[x]/ICH_LRC[x] (x>3) are UNDEFINED.

Configurations

AArch64 System register ICH_VTR_EL2 is architecturally mapped to AArch32 System register ICH_VTR.

If EL2 is not implemented, all bits in this register are RES0 from EL3, except for nV4, which is RES1 from EL3.

Bit fields and details that are not provided in this description are architecturally defined. See the Arm® Generic Interrupt Controller Architecture Specification.

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