B1.24 CPUPSELR, CPU Private Selection Register

The CPUPSELR provides IMPLEMENTATION DEFINED configuration and control options for the core.

Bit field descriptions

CPUPSELR is a 32-bit register, and is part of the Implementation defined registers functional group.

Figure B1-20 CPUPSELR bit assignments
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Reserved, [31:0]
Reserved for Arm internal use.
Configurations

CPUPSELR is:

Usage constraints

Accessing the CPUPSELR

Arm recommends that you write to this register after a powerup reset, before the MMU is enabled.

Writing to this register might cause UNPREDICTABLE behaviors. Therefore, Arm strongly recommends that you do not modify this register unless directed by Arm.

This register can be read using MRC with the following syntax:

MRC <syntax>

This register can be written using MCR with the following syntax:

MCR <syntax>

This syntax is encoded with the following settings in the instruction encoding:

<syntax> coproc opc1 CRn CRm Opc2
p15, 6, <Rt>, c15, c8, 0 1111 110 1111 1000 000
Accessibility

This register is accessible in software as follows:

<syntax> Control Accessibility
E2H TGE NS EL0 EL1 EL2 EL3
p15, 6, <Rt>, c15, c8, 0 x x 0 - - n/a RW
p15, 6, <Rt>, c15, c8, 0 x 0 1 - - - RW
p15, 6, <Rt>, c15, c8, 0 x 1 1 - n/a - RW

'n/a' Not accessible. The core cannot be executing at this Exception level, so this access is not possible.

Traps and enables

For a description of the prioritization of any generated exceptions, see Exception priority order in the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile for exceptions taken to AArch32 state, and see Synchronous exception prioritization for exceptions taken to AArch64 state.

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