B1.13 ATTBCR, Auxiliary Translation Table Base Control Register

The ATTBCR determines the values of PBHA on page table walks memory access in EL1 translation regime.

Bit field descriptions

ATTBCR is a 32-bit register.

Figure B1-9 ATTBCR bit assignments
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[31:14]
RES0.
HWVAL160, [13]
Indicates the value of PBHA[1] on page table walks memory access targeting the base address defined by TTB1 if HWEN160 is set.
HWVAL159, [12]
Indicates the value of PBHA[0] on page table walks memory access targeting the base address defined by TTB1 if HWEN159 is set.
[11:10]
RES0.
HWVAL060, [9]
Indicates the value of PBHA[1] page table walks memory access targeting the base address defined by TTB0 if HWEN060 is set.
HWVAL059, [8]
Indicates the value of PBHA[1] page table walks memory access targeting the base address defined by TTB0 if HWEN059 is set.
[7:6]
RES0.
HWEN160, [5]
Enables PBHA[1] page table walks memory access targeting the base address defined by TTB1. If this bit is clear, PBHA[1] on page table walks is 0.
HWEN159, [4]
Enables PBHA[0] page table walks memory access targeting the base address defined by TTB1. If this bit is clear, PBHA[0] on page table walks is 0.
[3:2]
RES0.
HWEN060, [1]
Enables PBHA[1] page table walks memory access targeting the base address defined by TTB0. If this bit is clear, PBHA[1] on page table walks is 0.
HWEN059, [0]
Enables PBHA[0] page table walks memory access targeting the base address defined by TTB0. If this bit is clear, PBHA[0] on page table walks is 0.
Configurations

AArch32 ATTBCR(NS) is architecturally mapped to AArch64 register ATCR_EL1.

AArch32 ATTBCR(S) is architecturally mapped to AArch64 register ATCR_EL3.

If EL3 is using AArch32, there are separate Secure and Non-secure instances of this register.

On a Warm reset, the Secure instance of ATTBCR resets to 0x0.

Usage constraints

Accessing the ATTBCR

This register can be read using MRC with the following syntax:

MRC <syntax>

This register can be written using MCR with the following syntax:

MCR <syntax>
<Syntax> coproc opc1 CRn CRm ocp2
p15, 0, <Rt>, c15, c7, 0 1111 000 1111 0111 000
Accessibility

If EL3 is implemented and is using AArch32, there are separate instances of this register and ATTBCR is accessible as follows:

<syntax> Control Accessibility Instance
E2H TGE NS EL0 EL1 EL2 EL3
p15, 0, <Rt>, c15, c7, 0 x x 0 - RW n/a RW SCTLR_S
p15, 0, <Rt>, c15, c7, 0 x 0 1 - RW RW RW SCTLR_NS
p15, 0, <Rt>, c15, c7, 0 x 1 1 - n/a RW RW SCTLR_NS
Traps and enables
Rules of trap and enable for this register are the same as TTBCR. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.
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