B3.7 ERR0PFGCDNR, Error Pseudo Fault Generation Count Down Register

ERR0PFGCDNR is the Cortex®-A55 node register that generates one of the errors that are enabled in the corresponding ERR0PFGCTL register.

Bit field descriptions

ERR0PFGCDNR is a 32-bit read/write register.

Figure B3-4 ERR0PFGCDNR bit assignments
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CDN, [31:0]
Count Down value. The reset value of the Error Generation Counter is used for the countdown.

There are no configuration options.

ERR0PFGCDNR resets to 0x00000000.

ERR0PFGCDNR is accessible from the following registers when ERRSELR.SEL==0:

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