B2.73 ID_ISAR6_EL1, AArch32 Instruction Set Attribute Register 6, EL1

The ID_ISAR6_EL1 provides information about the instruction sets that the core implements.

Bit field descriptions

ID_ISAR6_EL1 is a 32-bit register, and is part of the Identification registers functional group.

This register is Read Only.

Figure B2-59 ID_ISAR6_EL1 bit assignments
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RES0, [31:8]
DP, [7:4]

UDOT and SDOT instructions. The value is:

0b0001UDOT and SDOT instructions are implemented.
RES0, [3:0]

ID_ISAR6_EL1 is architecturally mapped to AArch32 register ID_ISAR6. See B1.67 ID_ISAR6, Instruction Set Attribute Register 6.

There is one copy of this register that is used in both Secure and Non-secure states.

ID_ISAR6_EL1 must be interpreted with ID_ISAR0_EL1, ID_ISAR1_EL1, ID_ISAR2_EL1, ID_ISAR3_EL1, ID_ISAR4_EL1, and ID_ISAR5_EL1. See:

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

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