B2.2 AArch64 architectural system register summary

This section describes the AArch64 architectural system registers implemented in the Cortex®-A55 core.

The section contains two tables:

Registers with implementation defined bit fields

This table identifies the architecturally defined registers in Cortex-A55 that have implementation defined bit fields. The register descriptions for these registers only contain information about the implementation defined bits.

See Table   B2-1 Registers with implementation defined bit fields.

Other architecturally defined registers

This table identifies the other architecturally defined registers that are implemented in the Cortex-A55 core. These registers are described in the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

See Table   B2-2 Other architecturally defined registers.

Table B2-1 Registers with implementation defined bit fields

Name Op0 CRn Op1 CRm Op2 Width Description
ACTLR_EL1 3 c1 0 c0 1 64 B2.5 ACTLR_EL1, Auxiliary Control Register, EL1
ACTLR_EL2 3 c1 4 c0 1 64 B2.6 ACTLR_EL2, Auxiliary Control Register, EL2
ACTLR_EL3 3 c1 6 c0 1 64 B2.7 ACTLR_EL3, Auxiliary Control Register, EL3
AIDR_EL1 3 c0 1 c0 7 32 B2.14 AIDR_EL1, Auxiliary ID Register, EL1
AFSR0_EL1 3 c5 0 c1 0 32 B2.8 AFSR0_EL1, Auxiliary Fault Status Register 0, EL1
AFSR0_EL2 3 c5 4 c1 0 32 B2.9 AFSR0_EL2, Auxiliary Fault Status Register 0, EL2
AFSR0_EL3 3 c5 6 c1 0 32 B2.10 AFSR0_EL3, Auxiliary Fault Status Register 0, EL3
AFSR1_EL1 3 c5 0 c1 1 32 B2.11 AFSR1_EL1, Auxiliary Fault Status Register 1, EL1
AFSR1_EL2 3 c5 4 c1 1 32 B2.12 AFSR1_EL2, Auxiliary Fault Status Register 1, EL2
AFSR1_EL3 3 c5 6 c1 1 32 B2.13 AFSR1_EL3, Auxiliary Fault Status Register 1, EL3
AMAIR_EL1 3 c10 0 c3 0 64 B2.15 AMAIR_EL1, Auxiliary Memory Attribute Indirection Register, EL1
AMAIR_EL2 3 c10 4 c3 0 64 B2.16 AMAIR_EL2, Auxiliary Memory Attribute Indirection Register, EL2
AMAIR_EL3 3 c10 6 c3 0 64 B2.17 AMAIR_EL3, Auxiliary Memory Attribute Indirection Register, EL3
CCSIDR_EL1 3 c0 1 c0 0 32 B2.23 CCSIDR_EL1, Cache Size ID Register, EL1
CLIDR_EL1 3 c0 1 c0 1 64 B2.24 CLIDR_EL1, Cache Level ID Register, EL1
CPACR_EL1 3 c1 0 c0 2 32 B2.25 CPACR_EL1, Architectural Feature Access Control Register, EL1
CPTR_EL2 3 c1 4 c1 2 32 B2.26 CPTR_EL2, Architectural Feature Trap Register, EL2
CPTR_EL3 3 c1 6 c1 2 32 B2.27 CPTR_EL3, Architectural Feature Trap Register, EL3
CSSELR_EL1 3 c0 2 c0 0 32 B2.36 CSSELR_EL1, Cache Size Selection Register, EL1
CTR_EL0 3 c0 3 c0 1 32 B2.37 CTR_EL0, Cache Type Register, EL0
DISR_EL1 3 c12 0 c1 1 64 B2.39 DISR_EL1, Deferred Interrupt Status Register, EL1
ERRIDR_EL1 3 c5 0 c3 0 32 B2.40 ERRIDR_EL1, Error ID Register, EL1
ERRSELR_EL1 3 c5 0 c3 1 32 B2.41 ERRSELR_EL1, Error Record Select Register, EL1
ERXADDR_EL1 3 c5 0 c4 3 64 B2.42 ERXADDR_EL1, Selected Error Record Address Register, EL1
ERXCTLR_EL1 3 c5 0 c4 1 64 B2.43 ERXCTLR_EL1, Selected Error Record Control Register, EL1
ERXFR_EL1 3 c5 0 c4 0 64 B2.44 ERXFR_EL1, Selected Error Record Feature Register, EL1
ERXMISC0_EL1 3 c5 0 c5 0 64 B2.45 ERXMISC0_EL1, Selected Error Record Miscellaneous Register 0, EL1
ERXMISC1_EL1 3 c5 0 c5 1 64 B2.46 ERXMISC1_EL1, Selected Error Record Miscellaneous Register 1, EL1
ERXSTATUS_EL1 3 c5 0 c4 2 32 B2.50 ERXSTATUS_EL1, Selected Error Record Primary Status Register, EL1
ESR_EL1 3 c5 0 c2 0 32 B2.51 ESR_EL1, Exception Syndrome Register, EL1
ESR_EL2 3 c5 4 c2 0 32 B2.52 ESR_EL2, Exception Syndrome Register, EL2
ESR_EL3 3 c5 6 c2 0 32 B2.53 ESR_EL3, Exception Syndrome Register, EL3
HACR_EL2 3 c1 4 c1 7 32 B2.54 HACR_EL2, Hyp Auxiliary Configuration Register, EL2
HCR_EL2 3 c1 4 c1 0 64 B2.55 HCR_EL2, Hypervisor Configuration Register, EL2
ID_AFR0_EL1 3 c0 0 c1 3 32 B2.65 ID_AFR0_EL1, AArch32 Auxiliary Feature Register 0, EL1
ID_DFR0_EL1 3 c0 0 c1 2 32 B2.66 ID_DFR0_EL1, AArch32 Debug Feature Register 0, EL1
ID_ISAR0_EL1 3 c0 0 c2 0 32 B2.67 ID_ISAR0_EL1, AArch32 Instruction Set Attribute Register 0, EL1
ID_ISAR1_EL1 3 c0 0 c2 1 32 B2.68 ID_ISAR1_EL1, AArch32 Instruction Set Attribute Register 1, EL1
ID_ISAR2_EL1 3 c0 0 c2 2 32 B2.69 ID_ISAR2_EL1, AArch32 Instruction Set Attribute Register 2, EL1
ID_ISAR3_EL1 3 c0 0 c2 3 32 B2.70 ID_ISAR3_EL1, AArch32 Instruction Set Attribute Register 3, EL1
ID_ISAR4_EL1 3 c0 0 c2 4 32 B2.71 ID_ISAR4_EL1, AArch32 Instruction Set Attribute Register 4, EL1
ID_ISAR5_EL1 3 c0 0 c2 5 32 B2.72 ID_ISAR5_EL1, AArch32 Instruction Set Attribute Register 5, EL1
ID_ISAR6_EL1 3 c0 0 c2 7 32 B2.73 ID_ISAR6_EL1, AArch32 Instruction Set Attribute Register 6, EL1
ID_MMFR0_EL1 3 c0 0 c1 4 32 B2.74 ID_MMFR0_EL1, AArch32 Memory Model Feature Register 0, EL1
ID_MMFR1_EL1 3 c0 0 c1 5 32 B2.75 ID_MMFR1_EL1, AArch32 Memory Model Feature Register 1, EL1
ID_MMFR2_EL1 3 c0 0 c1 6 32 B2.76 ID_MMFR2_EL1, AArch32 Memory Model Feature Register 2, EL1
ID_MMFR3_EL1 3 c0 0 c1 7 32 B2.77 ID_MMFR3_EL1, AArch32 Memory Model Feature Register 3, EL1
ID_MMFR4_EL1 3 c0 0 c2 6 32 B2.78 ID_MMFR4_EL1, AArch32 Memory Model Feature Register 4, EL1
ID_PFR0_EL1 3 c0 0 c1 0 32 B2.79 ID_PFR0_EL1, AArch32 Processor Feature Register 0, EL1
ID_PFR1_EL1 3 c0 0 c1 1 32 B2.80 ID_PFR1_EL1, AArch32 Processor Feature Register 1, EL1
ID_PFR2_EL1 3 c0 0 c3 4 32 B2.81 ID_PFR2_EL1, AArch32 Processor Feature Register 2, EL1
ID_AA64DFR0_EL1 3 c0 0 c5 0 64 B2.57 ID_AA64DFR0_EL1, AArch64 Debug Feature Register 0, EL1
ID_AA64ISAR0_EL1 3 c0 0 c6 0 64 B2.58 ID_AA64ISAR0_EL1, AArch64 Instruction Set Attribute Register 0, EL1
ID_AA64ISAR1_EL1 3 c0 0 c6 1 64 B2.59 ID_AA64ISAR1_EL1, AArch64 Instruction Set Attribute Register 1, EL1
ID_AA64MMFR0_EL1 3 c0 0 c7 0 64 B2.60 ID_AA64MMFR0_EL1, AArch64 Memory Model Feature Register 0, EL1
ID_AA64MMFR1_EL1 3 c0 0 c7 1 64 B2.61 ID_AA64MMFR1_EL1, AArch64 Memory Model Feature Register 1, EL1
ID_AA64MMFR2_EL1 3 c0 0 c7 2 64 B2.62 ID_AA64MMFR2_EL1, AArch64 Memory Model Feature Register 2, EL1
ID_AA64PFR0_EL1 3 c0 0 c4 0 64 B2.63 ID_AA64PFR0_EL1, AArch64 Processor Feature Register 0, EL1
ID_AA64PFR1_EL1 3 c0 0 c4 1 64 B2.64 ID_AA64PFR1_EL1, AArch64 Processor Feature Register 1, EL1
IFSR32_EL2 3 c5 4 c0 1 32 B2.82 IFSR32_EL2, Instruction Fault Status Register, EL2
LORC_EL1 3 c10 0 c4 3 64 B2.83 LORC_EL1, LORegion Control Register, EL1
LORID_EL1 3 c10 0 c4 7 64 B2.85 LORID_EL1, Limited Order Region Identification Register, EL1
LORN_EL1 3 c10 0 c4 2 64 B2.86 LORN_EL1, LORegion Number Register, EL1
MDCR_EL3 3 c1 6 c3 1 32 B2.88 MDCR_EL3, Monitor Debug Configuration Register, EL3
MIDR_EL1 3 c0 0 c0 0 32 B2.89 MIDR_EL1, Main ID Register, EL1
MPIDR_EL1 3 c0 0 c0 5 64 B2.90 MPIDR_EL1, Multiprocessor Affinity Register, EL1
PAR_EL1 3 c7 0 c4 0 64 B2.91 PAR_EL1, Physical Address Register, EL1
RVBAR_EL3 3 c12 6 c0 1 64 B2.93 RVBAR_EL3, Reset Vector Base Address Register, EL3
REVIDR_EL1 3 c0 0 c0 6 32 B2.92 REVIDR_EL1, Revision ID Register, EL1
SCTLR_EL1 3 c1 0 c0 0 32 B2.94 SCTLR_EL1, System Control Register, EL1
SCTLR_EL3 3 c1 6 c0 0 32 B2.96 SCTLR_EL3, System Control Register, EL3
TCR_EL1 3 c2 0 c0 2 64 B2.97 TCR_EL1, Translation Control Register, EL1
TCR_EL2 3 c2 4 c0 2 64 B2.98 TCR_EL2, Translation Control Register, EL2
TCR_EL3 3 c2 6 c0 2 64 B2.99 TCR_EL3, Translation Control Register, EL3
TTBR0_EL1 3 c2 0 c0 0 64 B2.100 TTBR0_EL1, Translation Table Base Register 0, EL1
TTBR0_EL2 3 c2 4 c0 0 64 B2.101 TTBR0_EL2, Translation Table Base Register 0, EL2
TTBR0_EL3 3 c2 6 c0 0 64 B2.102 TTBR0_EL3, Translation Table Base Register 0, EL3
TTBR1_EL1 3 c2 0 c0 1 64 B2.103 TTBR1_EL1, Translation Table Base Register 1, EL1
TTBR1_EL2 3 c2 4 c0 1 64 B2.104 TTBR1_EL2, Translation Table Base Register 1, EL2
VDISR_EL2 3 c12 4 c1 1 64 B2.105 VDISR_EL2, Virtual Deferred Interrupt Status Register, EL2
VSESR_EL2 3 c5 4 c2 3 64 B2.108 VSESR_EL2, Virtual SError Exception Syndrome Register
VTCR_EL2 3 c2 4 c1 2 32 B2.109 VTCR_EL2, Virtualization Translation Control Register, EL2
VTTBR_EL2 3 c2 4 c1 0 64 B2.110 VTTBR_EL2, Virtualization Translation Table Base Register, EL2

Table B2-2 Other architecturally defined registers

Name Op0 CRn Op1 CRm Op2 Width Description
AFSR0_EL12 3 c5 5 1 0 32 Auxiliary Fault Status Register 0
AFSR1_EL12 3 c5 5 1 1 32 Auxiliary Fault Status Register 1
AMAIR_EL12 3 c10 5 c3 0 64 Auxiliary Memory Attribute Indirection Register
CNTFRQ_EL0 3 c14 3 0 0 32 Counter-timer Frequency register
CNTHCTL_EL2 3 c14 4 c1 0 32 Counter-timer Hypervisor Control register
CNTHP_CTL_EL2 3 c14 4 c2 1 32 Counter-timer Hypervisor Physical Timer Control register
CNTHP_CVAL_EL2 3 c14 4 c2 2 64 Counter-timer Hyp Physical CompareValue register
CNTHP_TVAL_EL2 3 c14 4 c2 0 32 Counter-timer Hyp Physical Timer TimerValue register
CNTHV_CTL_EL2 3 c14 4 c3 1 32 Counter-timer Virtual Timer Control register
CNTHV_CVAL_EL2 3 c14 4 c3 2 64 Counter-timer Virtual Timer CompareValue register
CNTHV_TVAL_EL2 3 c14 4 c3 0 32 Counter-timer Virtual Timer TimerValue register
CNTKCTL_EL1 3 c14 0 c1 0 32 Counter-timer Kernel Control register
CNTKCTL_EL12 3 c14 5 c1 0 32 Counter-timer Kernel Control register
CNTP_CTL_EL0 3 c14 3 c2 1 32 Counter-timer Physical Timer Control register
CNTP_CTL_EL02 3 c14 5 c2 1 32 Counter-timer Physical Timer Control register
CNTP_CVAL_EL0 3 c14 3 c2 2 64 Counter-timer Physical Timer CompareValue register
CNTP_CVAL_EL02 3 c14 5 c2 2 64 Counter-timer Physical Timer CompareValue register
CNTP_TVAL_EL0 3 c14 3 c2 0 32 Counter-timer Physical Timer TimerValue register
CNTP_TVAL_EL02 3 c14 5 c2 0 32 Counter-timer Physical Timer TimerValue register
CNTPCT_EL0 3 c14 3 c0 1 64 Counter-timer Physical Count register
CNTPS_CTL_EL1 3 c14 7 c2 1 32 Counter-timer Physical Secure Timer Control register
CNTPS_CVAL_EL1 3 c14 7 c2 2 64 Counter-timer Physical Secure Timer CompareValue register
CNTPS_TVAL_EL1 3 c14 7 c2 0 32 Counter-timer Physical Secure Timer TimerValue register
CNTV_CTL_EL0 3 c14 3 c3 1 32 Counter-timer Virtual Timer Control register
CNTV_CTL_EL02 3 c14 5 c3 1 32 Counter-timer Virtual Timer Control register
CNTV_CVAL_EL0 3 c14 3 c3 2 64 Counter-timer Virtual Timer CompareValue register
CNTV_CVAL_EL02 3 c14 5 c3 2 64 Counter-timer Virtual Timer CompareValue register
CNTV_TVAL_EL0 3 c14 3 c3 0 32 Counter-timer Virtual Timer TimerValue register
CNTV_TVAL_EL02 3 c14 5 c3 0 32 Counter-timer Virtual Timer TimerValue register
CNTVCT_EL0 3 c14 3 c0 2 64 Counter-timer Virtual Count register
CNTVOFF_EL2 3 c14 4 c0 3 64 Counter-timer Virtual Offset register
CONTEXTIDR_EL1 3 c13 0 c0 1 32 Context ID Register (EL1)
CONTEXTIDR_EL12 3 c13 5 c0 1 32 Context ID Register (EL12)
CONTEXTIDR_EL2 3 c13 4 c0 1 32 Context ID Register (EL2)
CPACR_EL12 3 c1 5 c0 2 32 Architectural Feature Access Control Register
CPTR_EL3 3 c1 6 c1 2 32 Architectural Feature Trap Register (EL3)
DACR32_EL2 3 c3 4 c0 0 32 Domain Access Control Register
ESR_EL12 3 c5 5 c2 0 32 Exception Syndrome Register (EL12)
FAR_EL1 3 c6 0 c0 0 64 Fault Address Register (EL1)
FAR_EL12 3 c6 5 c0 0 64 Fault Address Register (EL12)
FAR_EL2 3 c6 4 c0 0 64 Fault Address Register (EL2)
FAR_EL3 3 c6 6 c0 0 64 Fault Address Register (EL3)
FPEXC32_EL2 3 c5 4 c3 0 32 Floating-point Exception Control register
HPFAR_EL2 3 c6 4 c0 4 64 Hypervisor IPA Fault Address Register
HSTR_EL2 3 c1 4 c1 3 32 Hypervisor System Trap Register
ID_AA64AFR0_EL1 3 c0 0 c5 4 64 AArch64 Auxiliary Feature Register 0
ID_AA64AFR1_EL1 3 c0 0 c5 5 64 AArch64 Auxiliary Feature Register 1
ID_AA64DFR1_EL1 3 c0 0 c5 1 64 AArch64 Debug Feature Register 1
ISR_EL1 3 c12 0 c1 0 32 Interrupt Status Register
LOREA_EL1 3 c10 0 c4 1 64 LORegion End Address Register
LORSA_EL1 3 c10 0 c4 0 64 LORegion Start Address Register
MAIR_EL1 3 c10 0 c2 0 64 Memory Attribute Indirection Register (EL1)
MAIR_EL12 3 c10 5 c2 0 64 Memory Attribute Indirection Register (EL12)
MAIR_EL2 3 c10 4 c2 0 64 Memory Attribute Indirection Register (EL2)
MAIR_EL3 3 c10 6 c2 0 64 Memory Attribute Indirection Register (EL3)
MDCR_EL2 3 c1 4 c1 1 32 Monitor Debug Configuration Register
MVFR0_EL1 3 c0 0 c3 0 32 AArch32 Media and VFP Feature Register 0
MVFR1_EL1 3 c0 0 c3 1 32 AArch32 Media and VFP Feature Register 1
MVFR2_EL1 3 c0 0 c3 2 32 AArch32 Media and VFP Feature Register 2
RMR_EL3 3 c12 6 c0 2 32 Reset Management Register
SCR_EL3 3 c1 6 c1 0 32 Secure Configuration Register
SCTLR_EL12 3 c1 5 c0 0 32 System Control Register (EL12)
SCTLR_EL2 3 c1 4 c0 0 32 System Control Register (EL2)
SDER32_EL3 3 c1 6 c1 1 32 AArch32 Secure Debug Enable Register
TCR_EL12 3 c2 5 c0 2 64 Translation Control Register (EL12)
TPIDR_EL0 3 c13 3 c0 2 64 EL0 Read/Write Software Thread ID Register
TPIDR_EL1 3 c13 0 c0 4 64 EL1 Software Thread ID Register
TPIDR_EL2 3 c13 4 c0 2 64 EL2 Software Thread ID Register
TPIDR_EL3 3 c13 6 c0 2 64 EL3 Software Thread ID Register
TPIDRRO_EL0 3 c13 3 c0 3 64 EL0 Read-Only Software Thread ID Register
TTBR0_EL12 3 c2 5 c0 0 64 Translation Table Base Register 0 (EL12)
TTBR1_EL12 3 c2 5 c0 1 64 Translation Table Base Register 1 (EL12)
VBAR_EL1 3 c12 0 c0 0 64 Vector Base Address Register (EL1)
VBAR_EL12 3 c12 5 c0 0 64 Vector Base Address Register (EL12)
VBAR_EL2 3 c12 4 c0 0 64 Vector Base Address Register (EL2)
VBAR_EL3 3 c12 6 c0 0 64 Vector Base Address Register (EL3)
VMPIDR_EL2 3 c0 4 c0 5 64 Virtualization Multiprocessor ID Register
VPIDR_EL2 3 c0 4 c0 0 32 Virtualization Core ID Register
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