B4.4 ICC_AP1R0, Interrupt Controller Active Priorities Group 1 Register 0

The ICC_AP1R0 provides information about Group 1 active priorities.

Bit field descriptions

This register is a 32-bit register and is part of:

  • The GIC system registers functional group.
  • The GIC control registers functional group.

The core implements 5 bits of priority with 32 priority levels, corresponding to the 32 bits [31:0] of the register. The possible values for each bit are:

0x00000000No interrupt active. This is the reset value.
0x00000001Interrupt active for priority 0x0.
0x00000002Interrupt active for priority 0x8.
0x80000000Interrupt active for priority 0xF8.

There is one instance of this register that is used in both Secure and Non-secure states.

AArch32 System register ICC_AP1R0 is architecturally mapped to AArch64 System register ICC_AP1R0_EL1.

Details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

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