B4.25 ICC_AP0R0_EL1, Interrupt Controller Active Priorities Group 0 Register 0, EL1

The ICC_AP0R0_EL1 provides information about Group 0 active priorities.

Bit descriptions

This register is a 32-bit register and is part of:

  • The GIC system registers functional group.
  • The GIC control registers functional group.

The core implements 5 bits of priority with 32 priority levels, corresponding to the 32 bits [31:0] of the register. The possible values for each bit are:

0x00000000No interrupt active. This is the reset value.
0x00000001Interrupt active for priority 0x0.
0x00000002Interrupt active for priority 0x8.
...
0x80000000Interrupt active for priority 0xF8.
Configurations
AArch64 System register ICC_AP0R0_EL1 is architecturally mapped to AArch32 System register ICC_AP0R0.

Accessibility

The Cortex®-A55 core supports 5-bit interrupt priority or 32 possible pre-emptible priorities. Accesses to ICC_AP0R0_EL1 are UNDEFINED.

Details not provided in this description are architecturally defined. See the Arm® Generic Interrupt Controller Architecture Specification.

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