|Home > Register Descriptions > AArch32 system registers > CPUPMR, CPU Private Mask Register|
The CPUPMR provides IMPLEMENTATION DEFINED configuration and control options for the core.
CPUPMR is a 64-bit register, and is part of the Implementation defined registers functional group.
|Reserved for Arm internal use.|
Arm recommends that you write to this register after a powerup reset, before the MMU is enabled.
Writing to this register might cause UNPREDICTABLE behaviors. Therefore, Arm strongly recommends that you do not modify this register unless directed by Arm.
This register can be read using MRRC with the following syntax:
This register can be written using MCRR with the following syntax:
This syntax is encoded with the following settings in the instruction encoding:
|p15, 10, <Rt>, <Rt2>, c15||1111||1010||1111|
This register is accessible in software as follows:
|p15, 10, <Rt>, <Rt2>, c15||x||x||0||-||-||n/a||RW|
|p15, 10, <Rt>, <Rt2>, c15||x||0||1||-||-||-||RW|
|p15, 10, <Rt>, <Rt2>, c15||x||1||1||-||n/a||-||RW|
'n/a' Not accessible. The core cannot be executing at this Exception level, so this access is not possible.
For a description of the prioritization of any generated exceptions, see Exception priority order in the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile for exceptions taken to AArch32 state, and see Synchronous exception prioritization for exceptions taken to AArch64 state.