B4.41 ICH_AP0R0_EL2, Interrupt Controller Hyp Active Priorities Group 0 Register 0, EL2

The ICH_AP0R0_EL2 provides information about Group 0 active priorities for EL2.

Bit field descriptions

This register is a 32-bit register and is part of:

  • The GIC system registers functional group.
  • The Virtualization registers functional group.
  • The GIC host interface control registers functional group.

The core implements 5 bits of priority with 32 priority levels, corresponding to the 32 bits [31:0] of the register. The possible values for each bit are:

0x00000000No interrupt active. This is the reset value.
0x00000001Interrupt active for priority 0x0.
0x00000002Interrupt active for priority 0x8.
0x80000000Interrupt active for priority 0xF8.

AArch64 System register ICH_AP0R0_EL2 is architecturally mapped to AArch32 System register ICH_AP0R0.

If EL2 is not implemented, this register is RES0 from EL3.

Details that are not provided in this description are architecturally defined. See the Arm® Generic Interrupt Controller Architecture Specification.

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