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The CPUCFR provides configuration information for the core.
CPUCFR is a 32-bit register and is part of the Implementation registers functional group.
This register is Read Only.
Indicates whether the SCU is present or not. The value is:
|0||The SCU is present.|
Indicates whether ECC is present or not. The possible values are:
|0||ECC is not present.|
|1||ECC is present.|
CPUCFR is architecturally mapped to AArch64 register CPUCFR_EL1. See B2.29 CPUCFR_EL1, CPU Configuration Register, EL1.
This register can be read using MRC with the following syntax:
This syntax is encoded with the following settings in the instruction encoding:
|p15, 0, <Rt>, c15, c0, 0||1111||000||1111||0000||000|
This register is accessible in software as follows:
|p15, 0, <Rt>, c15, c0, 0||x||x||0||-||RO||n/a||RO|
|p15, 0, <Rt>, c15, c0, 0||x||0||1||-||RO||RO||RO|
|p15, 0, <Rt>, c15, c0, 0||x||1||1||-||n/a||RO||RO|
'n/a' Not accessible. The PE cannot be executing at this Exception level, so this access is not possible.