B1.19 CPUCFR, CPU Configuration Register

The CPUCFR provides configuration information for the core.

Bit field descriptions

CPUCFR is a 32-bit register and is part of the Implementation registers functional group.

This register is Read Only.

Figure B1-15 CPUCFR bit assignments
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RES0, [31:3]
SCU, [2]

Indicates whether the SCU is present or not. The value is:

0The SCU is present.
ECC, [1:0]

Indicates whether ECC is present or not. The possible values are:

0ECC is not present.
1ECC is present.

CPUCFR is architecturally mapped to AArch64 register CPUCFR_EL1. See B2.29 CPUCFR_EL1, CPU Configuration Register, EL1.

Usage constraints

Accessing the CPUCFR

This register can be read using MRC with the following syntax:

MRC <syntax>

This syntax is encoded with the following settings in the instruction encoding:

<syntax> coproc opc1 CRn CRm opc2
p15, 0, <Rt>, c15, c0, 0 1111 000 1111 0000 000

This register is accessible in software as follows:

<syntax> Control Accessibility
p15, 0, <Rt>, c15, c0, 0 x x 0 - RO n/a RO
p15, 0, <Rt>, c15, c0, 0 x 0 1 - RO RO RO
p15, 0, <Rt>, c15, c0, 0 x 1 1 - n/a RO RO

'n/a' Not accessible. The PE cannot be executing at this Exception level, so this access is not possible.

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