A8.5 Error synchronization barrier

The Error Synchronization Barrier (ESB) instruction synchronizes unrecoverable errors.

The RAS extension adds the ESB instruction used to synchronize unrecoverable errors. Unrecoverable errors are containable errors consumed by the core and not silently propagated.

The ESB instruction allows efficient isolation of errors:

  • The ESB instruction does not wait for completion of accesses that cannot generate an asynchronous external abort. For example, if all external aborts are handled synchronously or it is known that no such accesses are outstanding.
  • The ESB instruction does not order accesses and does not guarantee a pipeline flush.

All unrecoverable errors must be synchronized by an ESB instruction. The ESB instruction guarantees the following:

  • All unrecoverable errors that are generated before the ESB instruction have pended a System Error Interrupts (SEI) exception.
  • If a physical SEI is pended by or was pending before the ESB instruction is executed:
    • If the physical SEI is unmasked at the current Exception level, then it is taken before completion of the ESB instruction.
    • If the physical SEI is masked at the current Exception level, the pending SEI is cleared, the SEI syndrome is recorded in DISR/DISR_EL1, and DISR/DISR_EL1.A is set to 1. This indicates that the SEI was generated before the ESB by instructions that occur in program order.

The ESB instruction also guarantees the following:

  • SEIs generated before the ESB instruction are either taken before or at the ESB instruction, or are pended in DISR/DISR_EL1.
  • SEIs generated after the ESB are not pended in DISR/DISR_EL1.

This includes unrecoverable errors that are generated by instructions, translation table walks, and instructions fetches on the same core.

Note:

DISR/DISR_EL1 can only be accessed at EL1 or above. If EL2 is implemented and HCR/HCR_EL2.AMO is set to 1, then reads and writes of DISR/DISR_EL1 at Non-secure EL1 access VDISR/VDISR_EL2.

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