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The Error Synchronization Barrier (
ESB) instruction synchronizes unrecoverable errors.
The RAS extension adds the
instruction used to synchronize unrecoverable errors. Unrecoverable errors are
containable errors consumed by the core and not silently propagated.
ESB instruction allows efficient
isolation of errors:
ESBinstruction does not wait for completion of accesses that cannot generate an asynchronous external abort. For example, if all external aborts are handled synchronously or it is known that no such accesses are outstanding.
ESBinstruction does not order accesses and does not guarantee a pipeline flush.
All unrecoverable errors must be synchronized by an
ESB instruction. The
ESB instruction guarantees the following:
ESBinstruction have pended a System Error Interrupts (SEI) exception.
ESBinstruction is executed:
ESBby instructions that occur in program order.
ESB instruction also guarantees
ESBinstruction are either taken before or at the
ESBinstruction, or are pended in DISR/DISR_EL1.
This includes unrecoverable errors that are generated by instructions, translation table walks, and instructions fetches on the same core.
DISR/DISR_EL1 can only be accessed at EL1 or above. If EL2 is implemented and HCR/HCR_EL2.AMO is set to 1, then reads and writes of DISR/DISR_EL1 at Non-secure EL1 access VDISR/VDISR_EL2.