|Home > Functional description > Memory Management Unit > Translation table walks|
When the Cortex®-A55 core generates a memory access, the MMU:
In the case of an L2 TLB miss, the hardware does a translation table walk as long as the MMU is enabled, and the translation using the base register has not been disabled.
If the translation table walk is disabled for a particular base register, the core returns a Translation Fault. If the TLB finds a matching entry, it uses the information in the entry as follows.
The access permission bits and the domain determine if the access is permitted. If the matching entry does not pass the permission checks, the MMU signals a Permission fault. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile for details of Permission faults, including: