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The GIC CPU interface, when integrated with an external distributor component, is a resource for supporting and managing interrupts in a cluster system.
The GIC CPU interface hosts registers to mask, identify, and control states of interrupts forwarded to that core. There is a separate GIC CPU interface for each core in the system.
The Cortex®-A55 core implements the GIC CPU interface as described in the Arm® Generic Interrupt Controller Architecture Specification. This interfaces with an external GICv3 or GICv4 interrupt distributor component within the system.
The GICv4 architecture supports:
The GIC includes interrupt grouping functionality that supports:
This chapter describes only features that are specific to the Cortex-A55 core implementation.