A9.2 Bypassing the CPU interface

The GIC CPU interface is always implemented within the Cortex®-A55 core.

However, you can disable it if you assert the GICCDISABLE signal HIGH at reset. If the GIC is enabled, the input pins nVIRQ and nVFIQ must be tied off to HIGH. This is because the internal GIC CPU interface generates the virtual interrupt signals to the cores. The nIRQ and nFIQ signals are controlled by software, therefore there is no requirement to tie them HIGH. If you disable the GIC CPU interface, the input pins nVIRQ and nVFIQ can be driven by an external GIC in the SoC.

If the Cortex-A55 core is not integrated with an external GICv3 or GICv4 distributor component in the system, then you can disable the GIC CPU interface by asserting the GICCDISABLE signal HIGH at reset.

GIC system register access generates undefined instruction exceptions when the GICCDISABLE signal is HIGH.

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