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Each CPU interface block provides the interface for the Cortex®-A55 core that interfaces with a GIC distributor within the system.
The Cortex-A55 core only supports system register access to the GIC CPU interface registers. The following table lists the three types of GIC CPU interface system registers supported in the Cortex-A55 core.
Table B4-1 GIC CPU interface system register types supported in the Cortex-A55 core.
|Register prefix||Register type|
|ICC||Physical GIC CPU interface system registers.|
|ICV||Virtual GIC CPU interface system registers.|
|ICH||Virtual interface control system registers.|
Access to virtual GIC CPU interface system registers is only possible at Non-secure EL1.
Access to ICC registers or the equivalent ICV registers is determined by HCR_EL2. See B2.55 HCR_EL2, Hypervisor Configuration Register, EL2.
For more information on the CPU interface, see the Arm® Generic Interrupt Controller Architecture Specification.