B4.18 AArch32 virtual interface control system register summary

The following table lists the AArch32 virtual interface control system registers that have implementation defined bits.

See the Arm® Generic Interrupt Controller Architecture Specification for more information and a complete list of AArch32 virtual interface control system registers.

Name Op1 CRn CRm Op2 Type Description
ICH_AP0R0 4 12 8 0 RW B4.19 ICH_AP0R0, Interrupt Controller Hyp Active Priorities Group 0 Register 0
ICH_AP1R0 4 12 9 0 RW B4.20 ICH_AP1R0, Interrupt Controller Hyp Active Priorities Group 1 Register 0
ICH_HCR 4 12 11 0 RW B4.21 ICH_HCR, Interrupt Controller Hyp Control Register
ICH_LR0 4 12 12 0 RW Interrupt Controller List Registers 0-3. The Cortex®-A55 core implements four ICH_LR registers, as defined by ICH_VTR.ListRegs. Accesses to the rest of the ICH_LR registers are UNDEFINED.
ICH_LR1 4 12 12 1 RW
ICH_LR2 4 12 12 2 RW
ICH_LR3 4 12 12 3 RW
ICH_VTR 4 12 11 1 RO B4.22 ICH_VMCR, Interrupt Controller Virtual Machine Control Register
ICH_VMCR 4 12 11 7 RW B4.23 ICH_VTR, Interrupt Controller VGIC Type Register
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