B2.18 ATCR_EL1, Auxiliary Translation Control Register, EL1

The ATCR_EL1 determines the values of PBHA on page table walks memory access in EL1 translation regime.

Bit field descriptions

ATCR_EL1 is a 64-bit register.

Figure B2-14 ATCR_EL1 bit assignments
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[63:14]
RES0.
HWVAL160, [13]
Indicates the value of PBHA[1] on page table walks memory access targeting the base address defined by TTBR1_EL1 if HWEN160 is set.
HWVAL159, [12]
Indicates the value of PBHA[0] on page table walks memory access targeting the base address defined by TTBR1_EL1 if HWEN159 is set.
[11:10]
RES0.
HWVAL060, [9]
Indicates the value of PBHA[1] page table walks memory access targeting the base address defined by TTBR0_EL1 if HWEN060 is set.
HWVAL059, [8]
Indicates the value of PBHA[1] page table walks memory access targeting the base address defined by TTBR0_EL1 if HWEN059 is set.
[7:6]
RES0.
HWEN160, [5]
Enables PBHA[1] page table walks memory access targeting the base address defined by TTBR1_EL1. If this bit is clear, PBHA[1] on page table walks is 0.
HWEN159, [4]
Enables PBHA[0] page table walks memory access targeting the base address defined by TTBR1_EL1. If this bit is clear, PBHA[0] on page table walks is 0.
[3:2]
RES0.
HWEN060, [1]
Enables PBHA[1] page table walks memory access targeting the base address defined by TTBR0_EL1. If this bit is clear, PBHA[1] on page table walks is 0.
HWEN059, [0]
Enables PBHA[0] page table walks memory access targeting the base address defined by TTBR0_EL1. If this bit is clear, PBHA[0] on page table walks is 0.
Configurations

AArch64 register ATCR_EL1 is mapped to AArch32 register ATTBCR (NS).

At EL2 with HCR_EL2.E2H set, accesses to ATCR_EL1 are remapped to access ATCR_EL2.

Usage constraints

Accessing the ATCR_EL1

To access the ATCR_EL1:

MRS Xt , S< 3   0  c15   c7  0> ; Read ATCR_EL1 into Xt 
MSR S < 3   0  c15   c7  0 > , Xt   ; Write Xt to ATCR_EL1

This syntax is encoded with the following settings in the instruction encoding:

Op0 Op1 CRn CRm Op2
3 0 c15 c7 0
Accessibility

ATCR_EL1 is accessible as follows:

  Control Accessibility
E2H TGE NS EL0 EL1 EL2 EL3
ATCR_EL1 x x 0 - RW n/a RW
ATCR_EL1 0 0 1 - RW RW RW
ATCR_EL1 0 1 1 - n/a RW RW
ATCR_EL1 1 0 1 - RW ATCR_EL2 RW
ATCR_EL1 1 1 1 - n/a ATCR_EL2 RW

Note:

ATCR_EL1 is also accessible using ATCR_EL12 when HCR.EL2.E2H is set. See B2.19 ATCR_EL12 , Alias to Auxiliary Translation Control Register EL1.
Traps and enables
Rules of traps and enables for this register are the same as TCR_EL1. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.
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