B1.14 AVTCR, Auxiliary Virtualized Translation Control Register

The AVTCR determines the values of PBHA on stage 2 page table walks memory access in EL1 Non-secure translation regime if stage 2 is enabled.

Bit field descriptions

AVTCR is a 32-bit register.

Figure B1-10 AVTCR bit assignments
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[31:10]
RES0.
HWVAL60, [9]
Indicates the value of PBHA[1] page table walks memory access if HWEN60 is set.
HWVAL59, [8]
Indicates the value of PBHA[1] page table walks memory access if HWEN59 is set.
[7:2]
RES0.
HWEN60, [1]
Enables PBHA[1] page table walks memory access. If this bit is clear, PBHA[1] on page table walks is 0.
HWEN59, [0]
Enables PBHA[0] page table walks memory access. If this bit is clear, PBHA[0] on page table walks is 0.
Configurations

AArch32 register AVTCR is architecturally mapped to AArch64 register AVTCR_EL2.

Usage constraints

Accessing the AVTCR

This register can be read using MRC with the following syntax:

MRC <syntax>

This register can be written using MCR with the following syntax:

MCR <syntax>
Syntax coproc opc1 CRn CRm opc2
p15, 4, <Rt>, c15, c7, 1 1111 100 1111 0111 001
Accessibility

AVTCR is accessible as follows:

<syntax> Control Accessibility
E2H TGE NS EL0 EL1 EL2 EL3
p15, 4, <Rt>, c15, c7, 1 x x 0 - - n/a RW
p15, 4, <Rt>, c15, c7, 1 x 0 1 - - RW RW
p15, 4, <Rt>, c15, c7, 1 x 1 1 - n/a RW RW
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