B3.9 ERR0PFGFR, Error Pseudo Fault Generation Feature Register

The ERR0PFGFR is the Cortex®-A55 node register that defines which fault generation features are implemented.

Bit field descriptions

ERR0PFGFR is a 32-bit read-only register.

Figure B3-6 ERR0PFGFR bit assignments
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PFG, [31]

Pseudo Fault Generation. The possible values are:

0The node does not support fault injection.
1The node implements a fault injection mechanism.
R, [30]

Restartable bit. When it reaches zero, the Error Generation Counter restarts from the ERR0PFGCDN value or stops. The possible values are:

0The node does not support this feature.
1This feature is controllable.
[29:7]
Reserved, RES0.
CE, [6]
Corrected Error generation. The possible values are:
0The node does not support this feature.
1This feature is controllable.
DE, [5]
Deferred Error generation. The possible values are:
0The node does not support this feature.
1This feature is controllable.
UEO, [4]
Latent or Restartable Error generation. The possible values are:
0The node does not support this feature.
UER, [3]
Signaled or Recoverable Error generation. The possible values are:
0The node does not support this feature.
1This feature is controllable.
UEU, [2]
Unrecoverable Error generation. The possible values are:
0The node does not support this feature.
UC, [1]
Uncontainable Error generation. The possible values are:
0The node does not support this feature.
1This feature is controllable.
[0]
Reserved, RES0.
Configurations

There are no configuration notes.

ERR0PFGFR resets to 0xC000006E.

ERR0PFGFR is accessible from the following registers when ERRSELR.SEL==0:

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