B2.81 ID_PFR2_EL1, AArch32 Processor Feature Register 2, EL1

The ID_PFR2_EL1 provides information about the programmers model and architecture extensions supported by the core.

Bit field descriptions

ID_PFR2_EL1 is a 32-bit register, and is part of the Identification registers functional group.

This register is Read Only.

Figure B2-67 ID_PFR2_EL1 bit assignments
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RES0, [31:8]
RES0 Reserved.
SSBS, [7:4]

AArch32 provides the PSTATE.SSBS mechanism to mark regions that are Speculative Store Bypassing Safe (SSBS).

CSV3, [3:0]

Data loaded under speculation with a permission or domain fault cannot be used to form an address or generate condition codes to be used by instructions newer than the load in the speculative sequence. This is the reset value.


There are no configuration notes.

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