B3.8 ERR0PFGCTLR, Error Pseudo Fault Generation Control Register

The ERR0PFGCTLR is the Cortex®-A55 node register that enables controlled fault generation.

Bit field descriptions

ERR0PFGCTLR is a 32-bit read/write register.

Figure B3-5 ERR0PFGCTLR bit assignments
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CDNEN, [31]

Count down enable. This bit controls transfers from the value held in the ERR0PFGCDNR into the Error Generation Counter and enables this counter to start counting down. The possible values are:

0

The Error Generation Counter is disabled.

1The value held in the ERR0PFGCDNR register is transferred into the Error Generation Counter. The Error Generation Counter counts down.
R, [30]

Restartable bit. When it reaches 0, the Error Generation Counter restarts from the ERR0PFGCDNR value or stops. The possible values are:

0When it reaches 0, the counter stops.
1When it reaches 0, the counter reloads the value stored in ERR0PFGCDNR and starts counting down again.
RES0, [29:7]
RES0Reserved.
CE, [6]

Corrected error generation enable. The possible values are:

0

No corrected error is generated.

1A corrected error is generated on the next instruction that could trigger such an error.
DE, [5]

Deferred Error generation enable. The possible values are:

0No deferred error is generated.
1A deferred error is generated on the next instruction that could trigger such an error.
RES0, [4]
RES0Reserved.
UER, [3]

Signaled or Recoverable Error generation enable. This bit controls whether a signaled or a recoverable error might be generated. The possible values are:

0No signaled or recoverable error will be generated.
1A signaled or a recoverable error is generated on the next instruction that could trigger such an error.
RES0, [2]
RES0Reserved.
UC, [1]

Uncontainable error generation enable. The possible values are:

0

No uncontainable error is generated.

1An uncontainable error is generated on the next instruction that could trigger such an error.
[0]
Reserved, RES0.
Configurations

There are no configuration notes.

ERR0PFGCTLR resets to 0x00000000.

ERR0PFGCTLR is accessible from the following registers when ERRSELR.SEL==0:

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