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If the SCTLR.C bit is set to 0, load and store instructions do not access any of the L1 data, L2, or DSU L3 caches.
The SCTLR.C bit controls whether accesses from the core can look up and allocate into the data cache and unified L2 or L3 caches. Data cache maintenance operations execute normally, regardless of how the SCTLR.C bit is set.
If the SCTLR.C bit is set to 0, then the following apply:
The L2 and L1 data caches cannot be disabled independently.