B1.38 ERXMISC0, Selected Error Miscellaneous Register 0

Register ERXMISC0 accesses bits [31:0] of the ERR<n>MISC0 control register for the error record selected by ERRSELR.SEL.

If ERRSELR.SEL==0, then ERXMISC0 accesses bits [31:0] of the ERR0MISC0 register for the core error record. See B3.5 ERR0MISC0, Error Record Miscellaneous Register 0.

If ERRSELR.SEL==1, then ERXMISC0 accesses bits [31:0] of the ERR1MISC0 register for the DSU error record. See the Arm® DynamIQ™ Shared Unit Technical Reference Manual.

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